Introduction to Spintronics by Aurélien Manchon (2020) giant magnetoresistance section
. Source. Describes how giant magnetoresistance was used in magnetoresistive disk heads in the 90's providing a huge improvement in disk storage density over the pre-existing inductive sensors
More comments at: Video "Introduction to Spintronics by Aurélien Manchon (2020)".
One argument of why, is that if you could travel faster than light, then you could send a message to a point in Spacetime that is spacelike-separated from the present. But then since the target is spacelike separated, there exists a inertial frame of reference in which that event happens before the present, which would be hard to make sense of.
RSA vs Diffie-Hellman key exchange are the dominant public-key cryptography systems as of 2020, so it is natural to ask how they compare:
- security.stackexchange.com/questions/35471/is-there-any-particular-reason-to-use-diffie-hellman-over-rsa-for-key-exchange
- crypto.stackexchange.com/questions/2867/whats-the-fundamental-difference-between-diffie-hellman-and-rsa
- crypto.stackexchange.com/questions/797/is-diffie-hellman-mathematically-the-same-as-rsa
As its name indicates, Diffie-Hellman key exchange is a key exchange algorithm. TODO verify: this means that in order to transmit a message, both parties must first send data to one another to reach a shared secret key. For RSA on the other hand, you can just take the public key of the other party and send encrypted data to them, the receiver does not need to send you any data at any point.
Determines energy. This comes out directly from the resolution of the Schrödinger equation solution for the hydrogen atom where we have to set some arbitrary values of energy by separation of variables just like we have to set some arbitrary numbers when solving partial differential equations with the Fourier series. We then just happen to see that only certain integer values are possible to satisfy the equations.
React setups:
Information about ARM paging can be found at: cirosantilli.com/linux-kernel-module-cheat#arm-paging
Those page faults only happen when a process tries to write to the page, and not read from it.
When Linux forks a process:
- instead of copying all the pages, which is unnecessarily costly, it makes the page tables of the two process point to the same physical address.
- it marks those linear addresses as read-only
- whenever one of the processes tries to write to a page, the makes a copy of the physical memory, and updates the pages of the two process to point to the two different physical addresses
x86 Paging Tutorial Multiple addresses translate to a single physical address by 
Ciro Santilli 37 Updated 2025-07-16
Ciro Santilli 37 Updated 2025-07-16The same linear address can translate to different physical addresses for different processes, depending only on the value inside
cr3.Both linear addresses
00002 000 from process 1 and 00004 000 from process 2 point to the same physical address 00003 000. This is completely allowed by the hardware, and it is up to the operating system to handle such cases.This often in normal operation because of Copy-on-write (COW), which be explained elsewhere.
Such mappings are sometime called "aliases".
x86 Paging Tutorial Multi-level paging scheme numerical translation example by Ciro Santilli 37 Updated 2025-07-16
Ciro Santilli 37 Updated 2025-07-16Page directory given to process by the OS:
entry index entry address page table address present
----------- ---------------- ------------------ --------
0 CR3 + 0 * 4 0x10000 1
1 CR3 + 1 * 4 0
2 CR3 + 2 * 4 0x80000 1
3 CR3 + 3 * 4 0
...
2^10-1 CR3 + 2^10-1 * 4 0Page tables given to process by the OS at
PT1 = 0x10000000 (0x10000 * 4K):entry index entry address page address present
----------- ---------------- ------------ -------
0 PT1 + 0 * 4 0x00001 1
1 PT1 + 1 * 4 0
2 PT1 + 2 * 4 0x0000D 1
... ...
2^10-1 PT1 + 2^10-1 * 4 0x00005 1Page tables given to process by the OS at where
PT2 = 0x80000000 (0x80000 * 4K):entry index entry address page address present
----------- --------------- ------------ ------------
0 PT2 + 0 * 4 0x0000A 1
1 PT2 + 1 * 4 0x0000C 1
2 PT2 + 2 * 4 0
...
2^10-1 PT2 + 0x3FF * 4 0x00003 1PT1 and PT2: initial position of page table 1 and page table 2 for process 1 on RAM.With that setup, the following translations would happen:
linear 10 10 12 split physical
-------- -------------- ----------
00000001 000 000 001 00001001
00001001 000 001 001 page fault
003FF001 000 3FF 001 00005001
00400000 001 000 000 page fault
00800001 002 000 001 0000A001
00801004 002 001 004 0000C004
00802004 002 002 004 page fault
00B00001 003 000 000 page faultLet's translate the linear address
0x00801004 step by step:- In binary the linear address is:
0 0 8 0 1 0 0 4 0000 0000 1000 0000 0001 0000 0000 0100 - Grouping as
10 | 10 | 12gives:which gives:0000000010 0000000001 000000000100 0x2 0x1 0x4So the hardware looks for entry 2 of the page directory.page directory entry = 0x2 page table entry = 0x1 offset = 0x4 - The page directory table says that the page table is located at
0x80000 * 4K = 0x80000000. This is the first RAM access of the process. - Finally, the paging hardware adds the offset, and the final address is
0x0000C004.
The Intel manual gives a picture of this translation process in the image "Linear-Address Translation to a 4-KByte Page using 32-Bit Paging": Figure 1. "x86 page translation process"
x86 page translation process
. 
Some notable ones:
There are unlisted articles, also show them or only show them.