React setups:
Information about ARM paging can be found at: cirosantilli.com/linux-kernel-module-cheat#arm-paging
Those page faults only happen when a process tries to write to the page, and not read from it.
When Linux forks a process:
- instead of copying all the pages, which is unnecessarily costly, it makes the page tables of the two process point to the same physical address.
- it marks those linear addresses as read-only
- whenever one of the processes tries to write to a page, the makes a copy of the physical memory, and updates the pages of the two process to point to the two different physical addresses
x86 Paging Tutorial Multiple addresses translate to a single physical address by 
Ciro Santilli 37 Updated 2025-07-11 +Created 1970-01-01
Ciro Santilli 37 Updated 2025-07-11 +Created 1970-01-01The same linear address can translate to different physical addresses for different processes, depending only on the value inside
cr3.Both linear addresses
00002 000 from process 1 and 00004 000 from process 2 point to the same physical address 00003 000. This is completely allowed by the hardware, and it is up to the operating system to handle such cases.This often in normal operation because of Copy-on-write (COW), which be explained elsewhere.
Such mappings are sometime called "aliases".
x86 Paging Tutorial Page size choice by Ciro Santilli 37 Updated 2025-07-11 +Created 1970-01-01
Ciro Santilli 37 Updated 2025-07-11 +Created 1970-01-01 x86 Paging Tutorial Multi-level paging scheme numerical translation example by Ciro Santilli 37 Updated 2025-07-11 +Created 1970-01-01
Ciro Santilli 37 Updated 2025-07-11 +Created 1970-01-01Page directory given to process by the OS:
entry index entry address page table address present
----------- ---------------- ------------------ --------
0 CR3 + 0 * 4 0x10000 1
1 CR3 + 1 * 4 0
2 CR3 + 2 * 4 0x80000 1
3 CR3 + 3 * 4 0
...
2^10-1 CR3 + 2^10-1 * 4 0Page tables given to process by the OS at
PT1 = 0x10000000 (0x10000 * 4K):entry index entry address page address present
----------- ---------------- ------------ -------
0 PT1 + 0 * 4 0x00001 1
1 PT1 + 1 * 4 0
2 PT1 + 2 * 4 0x0000D 1
... ...
2^10-1 PT1 + 2^10-1 * 4 0x00005 1Page tables given to process by the OS at where
PT2 = 0x80000000 (0x80000 * 4K):entry index entry address page address present
----------- --------------- ------------ ------------
0 PT2 + 0 * 4 0x0000A 1
1 PT2 + 1 * 4 0x0000C 1
2 PT2 + 2 * 4 0
...
2^10-1 PT2 + 0x3FF * 4 0x00003 1PT1 and PT2: initial position of page table 1 and page table 2 for process 1 on RAM.With that setup, the following translations would happen:
linear 10 10 12 split physical
-------- -------------- ----------
00000001 000 000 001 00001001
00001001 000 001 001 page fault
003FF001 000 3FF 001 00005001
00400000 001 000 000 page fault
00800001 002 000 001 0000A001
00801004 002 001 004 0000C004
00802004 002 002 004 page fault
00B00001 003 000 000 page faultLet's translate the linear address
0x00801004 step by step:- In binary the linear address is:
0 0 8 0 1 0 0 4 0000 0000 1000 0000 0001 0000 0000 0100 - Grouping as
10 | 10 | 12gives:which gives:0000000010 0000000001 000000000100 0x2 0x1 0x4So the hardware looks for entry 2 of the page directory.page directory entry = 0x2 page table entry = 0x1 offset = 0x4 - The page directory table says that the page table is located at
0x80000 * 4K = 0x80000000. This is the first RAM access of the process. - Finally, the paging hardware adds the offset, and the final address is
0x0000C004.
The Intel manual gives a picture of this translation process in the image "Linear-Address Translation to a 4-KByte Page using 32-Bit Paging": Figure 1. "x86 page translation process"
x86 page translation process
. Why do the up ad down quarks have different masses? by Ciro Santilli 37 Updated 2025-07-11 +Created 1970-01-01
Ciro Santilli 37 Updated 2025-07-11 +Created 1970-01-01
Some notable ones:
Each transaction isolation level specifies what can or cannot happen when two queries are being run in parallel, i.e.: the memory semantics of the system.
Remember that queries can affects thousands of rows, and database systems like PostgreSQL can run multiple such queries at the same time.
Implementation specifics:
PostgreSQL feels good.
Its feature set is insanely large! Just look at stuff like: stackoverflow.com/questions/1986491/sql-split-string-by-space-into-table-in-postgresql/1993058#1993058
If Oracle is the Microsoft of database, Postgres is the Linux, and MySQL (or more precisely MariaDB) is the FreeBSD (i.e. the one that got delayed by legal issues). Except that their software licenses were accidentally swapped.
The only problem with Postgres is its name. PostgreSQL is so unpronounceable and so untypeable that you should just call it "Postgres" like everyone else.
What is spintronics and how is it useful? by SciToons (2019)
Source. Gives a good 1 minute explanation of tunnel magnetoresistance.It is so mind blowing that people believed in this theory. How can you think that, when you turn on a lamp and then you see? Obviously, the lamp must be emitting something!!!
Then comes along this epic 2002 paper: pubmed.ncbi.nlm.nih.gov/12094435/ "Fundamentally misunderstanding visual perception. Adults' belief in visual emissions". TODO review methods...
A fundamental component of three-level lasers.
As mentioned at youtu.be/_JOchLyNO_w?t=581 from Video "How Lasers Work by Scientized (2017)", they stay in that state for a long time compared to non spontaneous emission of metastable states!
phys.libretexts.org/Courses/University_of_California_Davis/UCD%3A_Physics_9HE_-_Modern_Physics/06%3A_Emission_and_Absorption_of_Photons/6.3%3A_Lasers mentions that they are kept in that excited state due to selection rules.
This is also one of mechanisms behind phosphorescence with triplet states.
Do A Moonshot by Jack Hidary (2016)
Source. uknqt.ukri.org/wp-content/uploads/2021/10/UKNQTP-Strategic-Intent-2020.pdf page 24 mentions UKNQTP investment and gives an overview of some layers.
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