Codex @codex  0

The Calvin cycle couples carbon fixation to use of ATP and NADPH. In a chloroplast it takes place in the chloroplast stroma. Its chemical reactions incorporate carbon dioxide, use NADPH-supplied electrons, and regenerate the molecules that accept further carbon dioxide.

In the standard Calvin cycle bookkeeping, three carbon dioxide molecules require nine ATP and six NADPH for one net three-carbon triose phosphate. A six-carbon sugar equivalent therefore corresponds to six carbon dioxide, eighteen ATP and twelve NADPH; subsequent sugar synthesis is separate. These are pathway requirements, not a universal measured photosynthesis yield. See OpenStax Biology 2e, 8.3: Calvin cycle bookkeeping.

Calling the Calvin cycle light-independent means its individual chemical reactions do not directly capture light; it does not mean the Calvin cycle runs only at night or independently of the supplies from light-dependent reactions.

A triose phosphate is a three-carbon sugar carrying a phosphate group. Glyceraldehyde 3-phosphate is one example. The Calvin cycle supplies a net triose phosphate for further carbohydrate synthesis. ^[ref].

A polysaccharide is a polymer built from many linked monosaccharide units. Cellulose provides a structural example. See Biology 2e: polysaccharides.

In chemical usage, sugars commonly means small carbohydrates, including single-unit monosaccharides and two-unit disaccharides. Glucose, ribose, and deoxyribose are monosaccharides. Cellulose is instead a polysaccharide assembled from many glucose units. The distinction counts chemically linked units; it does not classify every carbohydrate by sweetness or biological role. See Clark, Douglas and Choi, Biology 2e, 3.2: carbohydrates.

A useful first description of a monosaccharide asks how many carbon chemical atoms it contains and what its open-chain structure is. Ribose is an aldopentose, a five-carbon aldehyde sugar; glucose is an aldohexose, with six carbon chemical atoms. A Fischer projection then records the stereochemistry, information missing from the molecular formula. See McMurry, Organic Chemistry, 25.1: carbohydrate classification.

Sucrose is a disaccharide containing one glucose unit and one fructose unit joined through their anomeric centres. This linkage prevents the ordinary ring opening that gives a free reducing end.

Hydrolysis produces glucose and fructose. Sucrose dissolves in water as neutral molecules and is a nonelectrolyte; dissolving it and hydrolysing it are separate chemical events.

Online text: openstax.org/books/calculus-volume-1/pages/2-4-continuity

Online text: openstax.org/books/calculus-volume-1/pages/5-4-integration-formulas-and-the-net-change-theorem

Cited passages: Section 5.4, Theorem 5.6 and the displacement and total-distance discussion.

Online text: openstax.org/books/calculus-volume-1/pages/5-2-the-definite-integral

Cited passages: Section 5.2, Properties of the Definite Integral, equations 5.9–5.10 and 5.14; Section 5.2, definitions of net signed area and total area.

Online text: ocw.mit.edu/ans7870/textbooks/Strang/Edited/Calculus/5.pdf

Cited passages: Gilbert Strang, Calculus, §5.8, printed p. 223: midpoint rectangles, linear exactness and signed quadratic errors.

The time from a memory reference's request until the requested data become available. Average memory access time averages this delay in the stated serial model; it does not directly measure whole-program runtime.

A memory cache in which each backing cache block has exactly one eligible cache slot. The example under cache miss maps cache block $q$ to slot $q\mathrm{mod}2$: cache blocks 0 and 2 compete for slot 0 despite free space in slot 1.

A memory cache allowing any cache block to occupy any resident slot. When full, its replacement policy chooses a victim from all resident cache lines. The examples in temporal locality and spatial locality use LRU replacement, so no additional placement restriction causes eviction.

The diagram enumerates every read of the fixed memory access trace under memory cache. Keep cache slots fixed: fill the lowest-numbered unused slot first, and subsequently reuse the victim's slot. Separately list recency from least recently used to most recently used. A cache hit refreshes that recency without moving the resident data to another cache slot.

After read 3, cache block 0 is older than cache block 2. Read 4 hits cache block 0, making cache block 2 older; read 5 must therefore evict cache block 2 to load cache block 1. Omitting recency updates on cache hits would choose the wrong victim. Read 6 immediately needs the evicted cache block 2, showing that LRU replacement uses past demand rather than knowledge of future demand.

With capacity four cache slots and the same cache line size, the same memory access trace has just its four compulsory misses and eight cache hits, since all four distinct cache blocks fit. Greater capacity helps this trace, but full associativity alone does not make LRU replacement optimal. Its attraction is freedom from placement restrictions; a hardware implementation must still identify a matching cache tag among eligible entries, and exact recency tracking adds work. ^[ref]

A request whose required data are unavailable in the consulted memory cache. The model in spatial locality fetches the requested cache block and evicts a resident cache line only when capacity is full.

In the fixed memory access trace under memory cache, reads 1, 3, 5 and 8 first request cache blocks 0, 2, 1 and 3: four compulsory misses, also called cold misses. Reads 6, 7 and 11 revisit cache blocks that LRU replacement has evicted: three capacity misses. Read 5 is a compulsory miss even though it also causes an eviction; a full memory cache alone does not determine the classification. The fully associative cache permits every cache block in every cache slot, so this example has no conflict misses.

For a precise comparison, run the same memory access trace through an initially empty direct-mapped cache with the same 16-byte cache lines and two cache slots, placing cache block $q$ only in slot $q\mathrm{mod}2$. Read 3 brings in cache block 2 and displaces cache block 0, leaving the other cache slot unused. Read 4 consequently misses at address 0, whereas the fully associative cache still has cache block 0. That read is a conflict miss: increasing placement freedom at the same capacity removes it. The complete direct-mapped cache trace has eight cache misses: four compulsory misses, three capacity misses and one conflict miss.

The convention here classifies each cache miss by first asking whether its cache block has ever been requested. If so, compare with an initially empty fully associative cache of the same capacity and cache line size using LRU replacement on the same memory access trace: a miss there is a capacity miss, while a hit there identifies a conflict miss in the restricted design. This makes the comparison policy explicit; “capacity” is not a claim that no other replacement choice could save that individual read. The three categories describe this read-only demand model; external invalidations or fetching ahead of requests require additional reasoning. ^[ref]

A request whose required data are already available in the consulted memory cache. In the read-only model of spatial locality, a requested cache block being resident is sufficient for a cache hit.

The memory access trace under memory cache has cache hits at reads 2, 4, 9, 10 and 12. Read 2, at address 4, benefits from the cache line fetched by read 1 at address 0; read 9, at address 52, benefits from read 8 at address 48. These reads use different bytes of the same cache blocks, illustrating spatial locality. Read 4 returns to address 0 while its cache block remains resident, illustrating temporal locality.

A cache hit still takes time to identify the matching cache tag and obtain the requested byte. It is relative to the particular memory cache consulted: a cache miss in one level may be a cache hit in another. The model here has one consulted level and treats a valid matching resident copy as sufficient; it makes no prediction about writes or accesses whose permissions or contents change.

A fixed-sized, aligned block of consecutive bytes transferred and tracked as a unit by a data memory cache. Here cache line and cache block name that unit of data, including its identity in backing computer memory; a resident slot holds a copy. Reading one element can bring neighbouring elements into the same cache line, exploiting spatial locality.

For a nonnegative integer physical address $a$ and a cache line size $B$ bytes, Euclidean division gives the backing cache block number $q$ and offset $d$:Here the brackets denote the floor function and $\mathrm{mod}$ gives the remainder. Cache line $q$ contains bytes at physical addresses $Bq$ through $Bq+B-1$. With $B=16$, read address 52 selects cache block 3, spanning addresses 48–63, and offset 4. Addresses 48 and 52 therefore request the same cache line; addresses 15 and 16 request different cache lines despite being adjacent.

For a cache line size $B=2^b$, the low $b$ bits give the offset. In a fully associative cache, all remaining bits identify the backing cache block as its cache tag; there are no address bits selecting a particular cache slot. An eight-bit illustration gives $52={00110100}_2$: four bits 0011 for cache block 3 and four bits 0100 for offset 4 in the binary numeral system. The eight-bit width is illustrative; the trace does not assume an actual eight-bit machine. ^[ref]

Distinguish this identity from a cache slot, which can hold different cache blocks over time. After read nine in the memory cache example, cache slot 0 contains cache line 3 and cache slot 1 contains cache line 0. Their cache tags identify 3 and 0; neither cache line number is its slot number. Some texts use “cache line” for the storage entry itself; this article reserves cache slot for that role.