Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 3

The following original schematic shows the two data organisations. Register-address, write-enable and memory controls are common background; the diagram highlights the changed combinational logic paths.

In the parallel design the result-source multiplexer selects either the arithmetic logic unit or barrel shifter. Its control is additional to the ALU function and shift amount. (i) Addition: read the two operands, select ALU addition and select the ALU result; the shift amount is irrelevant. (ii) Constant left bit shift: read the operand to be shifted, set the shift amount from the immediate operand and select the barrel shifter result; the ALU operation is irrelevant.

In the serial design the result comes through the ALU, so that result-source selection disappears. Its shift-amount control is now relevant to arithmetic as well. (i) Addition: set the barrel shifter to zero shift and select ALU addition, so its inputs are the unshifted processor register values. (ii) Constant left bit shift: set the requested shift and select an ALU operation that passes the shifted operand through. If the ALU lacks that operation, implement it or provide a selectable zero on its other input and add zero. This requirement should be stated, rather than assuming that an ordinary two-input add automatically performs a shift alone.

The ALU result can still supply the memory address. For a register-result instruction, enable processor register writeback and leave memory writes disabled. If the ISA requires shift carry flags, the flag-generation control must retain the barrel shifter's outgoing-bit information; blindly using a pass-through ALU's arithmetic carry is insufficient.

Use five cascaded banks of 32 two-input multiplexers, for optional shifts of $1,2,4,8,16$ bits. The original circuit schematic below shows one bank per shift-amount bit; this is a left bit shift with zero fill, not a bit rotation.

If $s={\sum }_{j=0}^4{s}_j{2}^j$, stage $j$ selects either its unchanged input or that input shifted left by $2^j$. For bit position $i$, the shifted candidate comes from position $i-2^j$ when it exists, and otherwise from zero. Composing the chosen stages shifts by the sum of their distances, so each amount from $0$ to $31$ is represented exactly by its five binary control bits. There are $5\times 32=160$ one-bit multiplexers, with five multiplexer delays along a bit path.

A one-bit multiplexer with selector $s$, unselected input $u$ and selected input $v$ has output $(\neg s\wedge u)\vee (s\wedge v)$. It can be made from one NOT gate, two AND gates and an OR gate; a bank can share the selector inversion. The two possible selector values directly verify its behaviour.

SP-relative addressing forms an effective memory address by adding an offset to the stack pointer. It accesses local variables, saved processor registers or other stack-frame data without dedicating a separate base processor register for each object. The supplied reference gives word-aligned SP-relative offsets from $0$ to $1020$, which corresponds to an eight-bit nonnegative field scaled by four.

In the modified datapath, select the stack pointer for the unshifted ALU input, the instruction immediate operand for the barrel shifter input, and ALU addition. The effective address can then be $\mathrm{SP}+(\mathrm{imm}\ll s)$. Scaling the immediate operand changes the reachable displacement range without storing a larger immediate operand. For example, an eight-bit field shifted by two reaches offsets through $255\times 4=1020$; shifting it by four reaches through $4080$, but only on a sixteen-byte grid. Larger range and finer address granularity are different properties, so the extra reach is not free arbitrary-byte addressing.

The parallel layout cannot feed a shifted immediate operand directly into its address-producing ALU in the same pass. The serial layout can. The actual immediate operand width and permitted shift encodings of a new instruction must be specified; the question does not fix them, so no particular enlarged instruction encoding is implied.

A useful additional mode is base plus scaled register indexing, with effective address $B+(I\ll s)$. For an array of four-byte elements choose $s=2$, use its base address on the unshifted ALU input and its index processor register on the barrel shifter input, then add. This forms an indexed machine word address in one datapath pass. An eight-byte element uses $s=3$.

With parallel ALU and barrel shifter outputs, shifting and adding require either separate instructions/cycles or another route from the barrel shifter to the ALU. The new serial connection supplies that route. This is an addressing mode capability, not a claim that the old instruction encoding already contains the new mode.

The likely effect in a single-cycle or unchanged pipeline-stage implementation is a longer combinational critical path and hence a lower maximum processor clock frequency. Previously the barrel shifter and ALU could work in parallel before result selection; the modified path can require both shift and addition before address or result use.

Ignoring common processor register and wiring delays, the relevant combinational logic contribution changes roughly from $\max (t_{\mathrm{ALU}},t_{\mathrm{shift}})+t_{\mathrm{mux}}$ to $t_{\mathrm{shift}}+t_{\mathrm{ALU}}$, with any additional input selection included as needed. The processor clock period must also cover processor register timing and the rest of the instruction path, potentially including memory access. Removing a multiplexer offsets some delay, so a numerical frequency change cannot be inferred without component timings. Pipelining, a faster implementation or another pre-existing bottleneck can alter the outcome; the changed serial dependence is the reason for the likely reduction.