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An addressing mode specifies how an instruction obtains an operand or forms an effective memory address. Examples include immediate operands, processor register operands, base-plus-displacement memory access and scaled processor register indexing.

A programming language expressing machine instructions through symbolic operation names, processor registers, labels and data directives. A concrete program must respect its instruction set's operand restrictions and the platform's calling convention.

A combinational logic circuit mapping a binary input code to selected output lines. In a one-of-$k$ register-address decoder, line $i$ is asserted exactly when the address equals $i$, optionally combined with an enable. This selects which processor register may capture a common write-data word.

A processor register whose incoming value a called subroutine must restore before returning if it modifies it. This lets a caller retain live values across calls, but the caller must in turn preserve its own caller's values when using these processor registers.

A processor register that a subroutine may overwrite. A caller retaining a live value in such a processor register must preserve it elsewhere before calling. Argument and result processor registers commonly have this role.

The agreement between a caller and a subroutine on argument and result placement, processor register preservation, and call stack organization. Callee-saved registers retain their incoming values across a call; caller-saved registers must be saved by the caller if their values are still needed afterwards.

A context switch transfers CPU execution from one operating-system process or software thread to another while preserving enough execution context for the suspended task to resume. The operating-system kernel saves the outgoing task's processor registers, including its resume program counter and stack pointer, and restores the incoming task's saved state. Hardware entry and software switching divide this work differently across architectures; the diagram groups them into logical save and load steps. During the transition the same CPU executes the operating-system kernel's scheduler and switching code. ^[ref]

For a schematic switch from A to B, let A's resume program counter be $p_A$, its stack pointer $u_A$, and one illustrative data processor register contain 7. B's saved values are $p_B,u_B,42$. Saving A retains $(p_A,u_A,7)$ in A's execution context; loading B establishes $(p_B,u_B,42)$ before B resumes. These are selected fields, not a complete architecture-specific execution context. Later restoring A recovers its 7 even though B has used the same physical processor register for 42.

The useful invariant is that each suspended task retains its own resume state, so another task's use of the processor registers does not erase it. This is what makes repeated turns under round-robin scheduling possible. Saving an execution context does not copy the entire address space. Switching between software threads of one operating-system process can retain the same address space; switching between operating-system processes with different address spaces may also require changing the memory management unit's translation context, such as the active page table and associated address space identifier, depending on the architecture. Their contents remain in computer memory. ^[ref]

Entering the operating-system kernel through an interrupt, synchronous processor exception or system call does not automatically imply a context switch to another task. The handler may return to the same task; process scheduling determines whether another runnable task should take over. A context switch consumes time, and a changed memory cache or translation lookaside buffer working environment can add subsequent costs. Those costs are excluded from the toy process scheduling timelines, which are calculations rather than operating system benchmarks. ^[ref][ref]

A datapath comprises the processor registers, functional units and connections through which instruction operands and results move. Control signals select operand sources, operations, memory access and processor register writeback. Connecting a barrel shifter before an arithmetic logic unit permits shift-and-add operations in one pass, but puts their delays in series.

A device register exposes a device's status, control or data to software. Its access semantics can include side effects: a status flag may need an explicit acknowledgement operation before another event is detectable. A device register is not necessarily a processor register. Memory-mapped input-output input-output is one way to access it.

A fixed-width collection of flip-flops storing a binary representation. A synchronous load-enabled digital register captures all its input bits on the active clock edge when load is asserted and otherwise retains its old value. One multiplexer before each D flip-flop can select new data or feedback from its old output. A processor register is a particular use inside a processor; temporary state in a standalone binary multiplier is another.

The ordering of the bytes of a multi-byte value in addressed memory. Little-endian storage puts the least significant byte at the lowest address; big-endian storage puts the most significant byte there. Logical shifts of a value already held in a processor register act on bit significance, independently of that storage convention.

State needed to resume a suspended execution stream, including saved processor registers and its position in a call stack. An operating-system kernel can keep parts in a per-task record and parts on a kernel call stack. An execution context identifies and preserves that stream's state; it is not a duplicate of all the computer memory reachable through its address space.

// Target: computer-science.bigb

A processor register or equivalent value designating a stable reference location within the current stack frame. Parameters, local variables and saved links can be accessed at fixed offsets from the frame pointer even if the evaluation stack changes height.

An immediate operand is a value encoded in an instruction rather than fetched from a processor register or a separate memory location. Its width and interpretation limit the available values; scaling an encoded field can trade address granularity for displacement range.

The programmer-visible machine instruction repertoire and its semantics, including accessible processor registers and permitted operand forms. Different processors can implement the same instruction set architecture using different internal designs.

A machine instruction that reads a value from computer memory into a processor register. A demand cache miss may delay its result; a software prefetch has no such architectural result.

Consider an original toy file system service in address space B and a client in address space A, on one CPU. The service holds a five-byte cached file containing LIME followed by a newline. The client already has service handle 9, permission to read that file, and a security capability to send requests to IPC endpoint E. Handle 9 is interpreted by the service; it is neither a virtual address nor an operating-system kernel object identifier. All relevant memory pages are resident, and this read needs no device driver.

This protocol is an illustrative design, not an actual seL4 file system interface. Its call/reply structure follows seL4's documented IPC: seL4_Call waits using reply authority, and small payloads can travel in processor registers. ^[ref]

An ordinary pointer in A refers to A's address space. Sending its numeric value does not make B's private computer memory appear there. This example explicitly transfers bytes. Sharing a mapped memory page instead would require intentional memory protection permissions and a protocol for ownership and synchronization; passing a pointer alone establishes neither.

The same IPC mechanism could carry WRITE, but this client could still be refused by the service's read-only handle policy. Conversely, possession of an IPC endpoint security capability permits communication without automatically granting access to every file the service manages. The separation of mechanism and policy appears twice: endpoint authority gates delivery, and the service's handle policy gates the requested operation.

A family of reduced instruction set computer architectures. The classic 32-bit integer encoding has five-bit processor register fields, while many branch and jump instructions execute a branch delay slot. These conventions differ from later revisions and must be stated when presenting assembly language.

For an $n$-bit unsigned dividend $a$ and positive divisor $b$, read the dividend bits from most to least significant. If the processed prefix is $p$, maintain $p=bQ+R$ with $0\le R<b$. Appending bit $d$ gives trial remainder $T=2R+d$; append quotient bit $[T\ge b]$ and replace the remainder by $T-b[T\ge b]$. This preserves the quotient–remainder identity.

The old dividend and new quotient can share one $n$-bit processor register: after $k$ iterations its value is $(a{2}^k\mathrm{mod}{2}^n)+Q_k$, where $Q_k<2^k$. The shifted dividend occupies the upper positions and the accumulated quotient occupies the lower positions, so no information is overwritten. The high processor register holds $R_k$. For an $n$-bit dividend the next trial remainder is no larger than the next prefix, hence fits in $n$ bits through the final iteration. This last bound is specific to the dividend width; it must not be assumed for unrestricted multiword dividends.

Use the following explicit tree notation for the intermediate representation. C(k) is a constant, R(r) a processor register, M(e) a word load from memory address e, ADD addition, and SHL(e,2) a left shift by two bits. MOVE(destination,source) assigns either a processor register or the computer memory word designated by M. Parentheses show complete tree structure, so these displays specify trees rather than already shared Directed acyclic graphs.

Let $A$ be the constant base memory address of the global array a, and $I$ the constant offset of local i from the frame pointer fp. Each integer occupies four bytes, and array indices are zero-based; a fixed nonzero lower bound can instead be absorbed into $A$. Local t is represented by R(t). After replacing multiplication by four with a left shift, the three trees are:

MOVE(R(t),
     M(ADD(C(A),
           SHL(M(ADD(C(A),
                     SHL(M(ADD(R(fp),C(I))),2))),2))))

MOVE(M(ADD(C(A),
           SHL(M(ADD(C(A),
                     SHL(M(ADD(R(fp),C(I))),2))),2))),
     M(ADD(C(A),SHL(M(ADD(R(fp),C(I))),2))))

MOVE(M(ADD(C(A),SHL(M(ADD(R(fp),C(I))),2))),
     R(t))

Every M(ADD(R(fp),C(I))) loads i; the next enclosing M loads a[i]; the outermost M in the first tree loads a[a[i]]. Each array index is converted to a byte offset by a left shift of two bits. The address rule used in all three trees is The source language's array bounds checks are omitted as requested.