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Anant Agarwal is a computer scientist and electrical engineer whose work includes computer architecture, multicore processors and circuit education. MIT's departmental profile lists computer architecture among his research areas, while his CSAIL profile describes work involving multicore computing and authorship of a circuits textbook.^[ref]

His identified MIT faculty page links an external portrait of Anant Agarwal.

The MIT lecture State and Memory by Anant Agarwal and Jeffrey Lang, jointly credited with Jeffrey Lang, connects analog stored state to computer memory. A capacitor can summarize prior input by one state quantity, such as stored electric charge $q=C{v}_C$; digital storage then adds a rule for distinguishing logical values. The slides explicitly introduce capacitor state, zero-input response, zero-state response and a one-bit memory abstraction.^[ref]

For an original physical-memory example, let a $1\mathrm{nF}$ capacitor initially hold $3\mathrm{V}$ and leak through a $1\mathrm{M\Omega }$ resistor. With no driving input,If a stipulated readout interprets values above $2\mathrm{V}$ as the stored high state, the ideal decay reaches that threshold afterThe initial stored electric charge is $3\mathrm{nC}$, but the logical interpretation also depends on leakage, the elapsed time and the decision threshold. This is a teaching model, not a specification for a particular memory chip.

The example exposes why merely retaining some electric charge is different from reliably retaining a bit. A practical memory circuit must preserve distinguishable states over the required interval and allow the state to be read. Agarwal and Lang's lecture uses the state concept to connect the circuit's dynamics with that information-storage task.

The capacitive bridging complex-error bandwidth is the largest frequency over which a receiving port preserves the source phasor within a specified complex relative gain error. The criterion includes phase shift as well as amplitude. A large DC input impedance alone cannot establish this bandwidth when input capacitance matters. The manufacturer's input models explicitly include resistive and capacitive paths.^[ref]

For the scalar impedance bridging with capacitive input model, assume a positive real source electrical resistance $R_s$, receiver resistance $R_{\mathrm{in}}>0$, and input capacitance $C_{\mathrm{in}}>0$ in parallel. Let $V_s$ be the unloaded source phasor. A voltage divider givesFor tolerance $0<\eta <1$, the complex relative gain error isIts square is strictly increasing in $x^2$, since its derivative is $(1+2g)/[(1+g{)}^2+x^2{]}^2>0$. Thus satisfying $E(f)\le \eta$ defines a continuous frequency interval starting at DC, whenever it is feasible. Rearranging givesThe DC error floor is ${\eta }_0=g/(1+g)$. If $\eta <{\eta }_0$, no frequency meets the tolerance; if $\eta ={\eta }_0$, only DC does. The boxed positive bandwidth applies when $\eta >{\eta }_0$.

For an original near-limit example, choose $R_s=10\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$ and $C_{\mathrm{in}}=100\mathrm{pF}$. Then $g=0.01$ and the DC error is about 0.9901 percent. A 1 percent full-complex tolerance leaves onlyAn amplitude-only 1 percent criterion, $|H|\ge 0.99$, instead allows about $2273.47\mathrm{Hz}$. The half-power (approximately $-3\mathrm{dB}$) signal bandwidth, relative to DC, is $(1+g)/(2\pi R_s{C}_{\mathrm{in}})\approx 160.75\mathrm{kHz}$. These are three distinct specifications of this same ideal model.

The square-root collapse of capacitive bridging bandwidth near the DC error floor follows by factoring the numerator:For fixed $g>0$ and $\eta \downarrow {\eta }_0$,This asymptotic equivalence explains the sharp loss of usable bandwidth when the resistive divider has already consumed nearly all the error allowance. Increasing $R_{\mathrm{in}}$ or reducing $R_s$ changes that floor; reducing only $C_{\mathrm{in}}$ rescales a feasible bandwidth but cannot remove infeasibility at DC.

The criterion also controls a complete waveform. Suppose a source waveform $v_s$ is both a square-integrable function and a bandlimited function, with spectrum supported where $|H-1|\le \eta$. For the corresponding zero-state response $v_L$, the Fourier transform of $v_L-v_s$ is $(H-1){\hat{v}}_s$. The Plancherel theorem, or the norm bound for a Fourier multiplier on L2, givesHere the Fourier transform uses the frequency-in-hertz convention, so the displayed Plancherel theorem has no extra normalization factor. This bound includes waveform changes caused by phase. It applies to the zero-state response of the stated frequency response. Any additional homogeneous solution from initially stored energy contributes its own error.

A bench check therefore needs both amplitude ratio and phase shift, with probe and cable capacitance included in the port model. Magnitude-only observations determine $|H|$ without determining $|1-H|$. The formula describes this chosen passive input network; additional amplifier dynamics require their own transfer function.

The zero-input response is the output due to a system's initial internal state when its externally applied input is set to zero. It describes memory left by earlier excitation. For a linear time-invariant system, linearity separates this from the zero-state response due to the subsequent input.

For constant matrices in $\dot{x}=Ax+Bu$, $y=Cx+Du$, setting $u=0$ and $x(0)=x_0$ givesThe matrix exponential solves the homogeneous state equation. With an arbitrary input, the complete solution adds the zero-state response:A zero initial output $C{x}_0=0$ alone does not establish that the whole state is zero.

For an RC circuit with capacitor difference $v(0)=V_0$ and no applied source, $RC\dot{v}+v=0$, so $v(t)=V_0{e}^{-t/(RC)}$. The capacitor energy falls as $C{V}_0^2{e}^{-2t/(RC)}/2$; the resistor receives the dissipated energy. The primary MIT lecture explicitly distinguishes the capacitor's initial state, zero external input and zero initial state.^[ref]

At a time constant $RC=2\mathrm{s}$ and $V_0=3\mathrm{V}$, the modeled difference after two seconds is $3/e\approx 1.104\mathrm{V}$. Zero input has not meant zero output or zero stored energy. A direct experiment charges the same capacitor to different known initial differences, removes the charging source and records the decay across a fixed resistor. The amplitudes should scale with $V_0$ while the normalized decay remains the same in the linear model.

A zero-input response need not decay in every system: an ideal undamped oscillator retains its initial motion, and an unstable homogeneous system can amplify a nonzero initial state. The transfer function describes the zero-state input-output map, so its product with a zero input cannot represent a separate nonzero initial-state contribution.