Rydberg formula Updated 2025-07-16
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Dragon Boat Festival Updated 2025-07-16
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List of computational problems Updated 2025-07-16
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Monster Raving Loony Party Updated 2025-07-16
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Video 1.
Monster Raving Loony Party Conference by Britclip
. Source.
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Python language feature Updated 2025-07-16
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Ciro Santilli's hardware / Lenovo ThinkPad P14s gen4 amd Updated 2026-01-30
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Bought: November 2023 during Black Friday sale for £1,323.00 to be Ciro Santilli's main personal laptop.
Six years after, and we are 2x on every key spec (except processor Hz ;-) at about 1/2 the price and 1/2 the weight (though smaller 14" screen for greater portability), so not bad! Customized to max out each hardware spec:
Specs:
Identifiers:
Upon arrival:
  • Weight: 1490 g
  • Charger weight: 323 g
  • Firmware according to sudo dmidecode -t bios:
    Vendor: LENOVO
Version: R2FET33W (1.13 )
Release Date: 09/08/2023
Buy research:
Log:
2024-01-17: firmware update:
Vendor: LENOVO
Version: R2FET36W (1.16 )
Release Date: 10/24/2023
Actually fixed performance mode: askubuntu.com/questions/604720/setting-to-high-performance/1343879#1343879
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ZynAddSubFX Updated 2025-07-16
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Contains a large database of instruments, and allows you to edit them. This is a fun toy.
Instruments are edited on a GUI. It is a multi-window program, and you open new windows from new windows from new windows, all filled with hundreds of virtual knobs that you drag with your keyboard, and which would be better done from textual software like Csound. It is a thing of beauty.
It does not seem possible to program arbitrary modular synthesizer circuits therefore. But if you understand additive synthesis and subtractive synthesis well, you can make some funky sounds with it.
It is basically a superset of all popular hardware synthesizers ever made.
Has its own built-in MIDI keyboard which is nice.
On Ubuntu 20.04 Version: 3.0.5:
sudo apt install zynaddsubfx
zynaddsubfx -O alsa
as per askubuntu.com/questions/220802/no-sound-zynaddsubfx-and-jack-wont-run/1297988#1297988
To do anything of interest, switch to the Advanced UI:
The UI is completely different form what is shown on the website as of 2020: zynaddsubfx.sourceforge.io/, it looks instead like: www.youtube.com/watch?v=iVPr6iUuO3g Maybe on the website it is the new zyn-fusion UI... www.reddit.com/r/linuxaudio/comments/bxn3ur/some_help_for_installing_zynfusion_zynaddsubfx/ so confusing.
And they have some crappy policy of asking for 45 USD for binary downloads.
Compiling from source:
git clone https://github.com/zynaddsubfx/zynaddsubfx
cd zynaddsubfx
git checkout a789866de4d45a784c1f4d95fcf5a1938347baef
sudo apt build-dep zynaddsubfx
mkdir build
cd build
cmake ..
make -j`nproc`
fails with:
Traceback (most recent call last):
  File "/usr/bin/cxxtestgen", line 7, in <module>
    import cxxtest.cxxtestgen
  File "/usr/share/cxxtest/cxxtest/__init__.py", line 33, in <module>
    from cxxtest.cxxtestgen import *
  File "/usr/share/cxxtest/cxxtest/cxxtestgen.py", line 18, in <module>
    import __release__
ModuleNotFoundError: No module named '__release__'
Ciro gives up for now.
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ZX-calculus Updated 2025-07-16
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How can we easily prove that that quantum circuit equals the state:
(1)
?
The naive way would be to just do the matrix multiplication as explained at Section "Quantum computing is just matrix multiplication".
However, ZX-calculus provides a simpler way.
And even more importantly, sometimes it is the only way, because in a real circuit, we would not be able to do the matrix multiplication
What we do in ZX-calculus is we first transform the original quantum circuit into a ZX graph.
This is always possible, because we can describe how to do the conversion simply for any of the Clifford plus T gates, which is a set of universal quantum gates.
Then, after we do this transformation, we can start applying further transformations that simplify the circuit.
It has already been proven that there is no efficient algorithm for this (TODO source, someone said P-sharp complete best case)
But it has been proven in 2017 that any possible equivalence between quantum circuits can be reached by modifying ZX-calculus circuits.
There are only 7 transformation rules that we need, and all others can be derived from those, universality.
So, we can apply those rules to do the transformation shown in Wikipedia:
Figure 1.
GHZ circuit as ZX-diagram
. Source.
and one of those rules finally tells us that that last graph means our desired state:
(2)
because it is a Z spider with and .
Video 1.
Working with PyZX by Aleks Kissinger (2019)
Source. This video appears to give amazing motivation on why you should care about ZX-calculus, it mentions
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Slack (software) Updated 2026-01-30
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Year 4 of the physics course of the University of Oxford Updated 2025-07-16
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Students choose only one of the Cx courses.
Then there are PhDs corresponding to each of them: www.ox.ac.uk/admissions/graduate/courses/mpls/physics
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Yang-Mills existence and mass gap Updated 2025-07-16
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Video 1.
Yang-Mills 1 by David Metzler (2011)
Source.
A bit disappointing, too high level, with very few nuggests that are not Googleable withing 5 minutes.
Breakdown:
Video 2.
Millennium Prize Problem: Yang Mills Theory by David Gross (2018)
Source. 2 hour talk at the Kavli Institute for Theoretical Physics. Too mathematical, 2021 Ciro can't make much out of it.
Video 3.
Lorenzo Sadun on the "Yang-Mills and Mass Gap" Millennium problem
. Source. Unknown year. He almost gets there, he's good. Just needed to be a little bit deeper.
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Xah Lee Updated 2025-07-16
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fuseki.net/home/List-of-Patreon-Subs-with-Justification.html describes him well:
Outsider, formerly homeless, extreme person interested in CS and culture. Self-publishes a website with thousands of tutorial / opinion pages. Possibly similar to Sam Sloan - extremely productive, wide interests, obsessive, and pretty disagreeable.
Homepage xahlee.org/ says:
Siphon my knowledge into your brain. Assimilate my sensibilities to your spine.
Nice Second brain vibe.
Figure 1.
Xah Lee with some weird statuettes of himself
. Source. 2019.
Let's see:
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x86 Paging Tutorial / Multiple addresses translate to a single physical address Updated 2025-07-16
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The same linear address can translate to different physical addresses for different processes, depending only on the value inside cr3.
Both linear addresses 00002 000 from process 1 and 00004 000 from process 2 point to the same physical address 00003 000. This is completely allowed by the hardware, and it is up to the operating system to handle such cases.
This often in normal operation because of Copy-on-write (COW), which be explained elsewhere.
Such mappings are sometime called "aliases".
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x86 Paging Tutorial / Linux kernel usage Updated 2025-07-16
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The Linux kernel makes extensive usage of the paging features of x86 to allow fast process switches with small data fragmentation.
There are also however some features that the Linux kernel might not use, either because they are only for backwards compatibility, or because the Linux devs didn't feel it was worth it yet.
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x86 Paging Tutorial / How the K-ary tree is used in x86 Updated 2025-07-16
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x86's multi-level paging scheme uses a 2 level K-ary tree with 2^10 bits on each level.
Addresses are now split as:
| directory (10 bits) | table (10 bits) | offset (12 bits) |
Then:
  • the top 10 bits are used to walk the top level of the K-ary tree (level0)
    The top table is called a "directory of page tables".
    cr3 now points to the location on RAM of the page directory of the current process instead of page tables.
    Page directory entries are very similar to page table entries except that they point to the physical addresses of page tables instead of physical addresses of pages.
    Each directory entry also takes up 4 bytes, just like page entries, so that makes 4 KiB per process minimum.
    Page directory entries also contain a valid flag: if invalid, the OS does not allocate a page table for that entry, and saves memory.
    Each process has one and only one page directory associated to it (and pointed to by cr3), so it will contain at least 2^10 = 1K page directory entries, much better than the minimum 1M entries required on a single-level scheme.
  • the next 10 bits are used to walk the second level of the K-ary tree (level1)
    Second level entries are also called page tables like the single level scheme.
    Page tables are only allocated only as needed by the OS.
    Each page table has only 2^10 = 1K page table entries instead of 2^20 for the single paging scheme.
    Each process can now have up to 2^10 page tables instead of 2^20 for the single paging scheme.
  • the offset is again not used for translation, it only gives the offset within a page
One reason for using 10 bits on the first two levels (and not, say, 12 | 8 | 12 ) is that each Page Table entry is 4 bytes long. Then the 2^10 entries of Page directories and Page Tables will fit nicely into 4Kb pages. This means that it faster and simpler to allocate and deallocate pages for that purpose.
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x86 Paging Tutorial / CAM Updated 2025-07-16
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Using the TLB makes translation faster, because the initial translation takes one access per TLB level, which means 2 on a simple 32 bit scheme, but 3 or 4 on 64 bit architectures.
The TLB is usually implemented as an expensive type of RAM called content-addressable memory (CAM). CAM implements an associative map on hardware, that is, a structure that given a key (linear address), retrieves a value.
Mappings could also be implemented on RAM addresses, but CAM mappings may required much less entries than a RAM mapping.
For example, a map in which:
  • both keys and values have 20 bits (the case of a simple paging schemes)
  • at most 4 values need to be stored at each time
could be stored in a TLB with 4 entries:
linear  physical
------  --------
00000   00001
00001   00010
00010   00011
FFFFF   00000
However, to implement this with RAM, it would be necessary to have 2^20 addresses:
linear  physical
------  --------
00000   00001
00001   00010
00010   00011
... (from 00011 to FFFFE)
FFFFF   00000
which would be even more expensive than using a TLB.
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Erdős number Updated 2025-10-27
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Discrete logarithm Updated 2025-10-27
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An important case is the discrete logarithm of the cyclic group in which the group is a cyclic group.
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x86 Paging Tutorial / 64-bit architectures Updated 2025-07-16
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64 bits is still too much address for current RAM sizes, so most architectures will use less bits.
x86_64 uses 48 bits (256 TiB), and legacy mode's PAE already allows 52-bit addresses (4 PiB). 56-bits is a likely future candidate.
12 of those 48 bits are already reserved for the offset, which leaves 36 bits.
If a 2 level approach is taken, the best split would be two 18 bit levels.
But that would mean that the page directory would have 2^18 = 256K entries, which would take too much RAM: close to a single-level paging for 32 bit architectures!
Therefore, 64 bit architectures create even further page levels, commonly 3 or 4.
x86_64 uses 4 levels in a 9 | 9 | 9 | 9 scheme, so that the upper level only takes up only 2^9 higher level entries.
The 48 bits are split equally into two disjoint parts:
----------------- FFFFFFFF FFFFFFFF
Top half
----------------- FFFF8000 00000000


Not addressable


----------------- 00007FFF FFFFFFFF
Bottom half
----------------- 00000000 00000000
A 5-level scheme is emerging in 2016: software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf which allows 52-bit addresses with 4k pagetables.
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x86 Paging Tutorial Updated 2025-07-19
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This tutorial explains the very basics of how paging works, with focus on x86, although most high level concepts will also apply to other instruction set architectures, e.g. ARM.
The goals are to:
  • demonstrate minimal concrete simplified paging examples that will be useful to those learning paging for the first time
  • explain the motivation behind paging
This tutorial was extracted and expanded from this Stack Overflow answer.
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