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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 4 / a / ii by

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 4 / a / i by

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 3 / e / Solution by

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The likely effect in a single-cycle or unchanged pipeline-stage implementation is a longer combinational critical path and hence a lower maximum processor clock frequency. Previously the barrel shifter and ALU could work in parallel before result selection; the modified path can require both shift and addition before address or result use.

Ignoring common processor register and wiring delays, the relevant combinational logic contribution changes roughly from

max (t_{ALU}, t_{shift}) + t_{mux}

t_{shift} + t_{ALU}

, with any additional input selection included as needed. The processor clock period must also cover processor register timing and the rest of the instruction path, potentially including memory access. Removing a multiplexer offsets some delay, so a numerical frequency change cannot be inferred without component timings. Pipelining, a faster implementation or another pre-existing bottleneck can alter the outcome; the changed serial dependence is the reason for the likely reduction.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 3 / d / Solution by

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A useful additional mode is base plus scaled register indexing, with effective address

B + (I ≪ s)

. For an array of four-byte elements choose

s = 2

, use its base address on the unshifted ALU input and its index processor register on the barrel shifter input, then add. This forms an indexed machine word address in one datapath pass. An eight-byte element uses

s = 3

With parallel ALU and barrel shifter outputs, shifting and adding require either separate instructions/cycles or another route from the barrel shifter to the ALU. The new serial connection supplies that route. This is an addressing mode capability, not a claim that the old instruction encoding already contains the new mode.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 3 / c / Solution by

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SP-relative addressing forms an effective memory address by adding an offset to the stack pointer. It accesses local variables, saved processor registers or other stack-frame data without dedicating a separate base processor register for each object. The supplied reference gives word-aligned SP-relative offsets from

0

1020

, which corresponds to an eight-bit nonnegative field scaled by four.

In the modified datapath, select the stack pointer for the unshifted ALU input, the instruction immediate operand for the barrel shifter input, and ALU addition. The effective address can then be $SP + (imm ≪ s)$ . Scaling the immediate operand changes the reachable displacement range without storing a larger immediate operand. For example, an eight-bit field shifted by two reaches offsets through

255 \times 4 = 1020

; shifting it by four reaches through

4080

, but only on a sixteen-byte grid. Larger range and finer address granularity are different properties, so the extra reach is not free arbitrary-byte addressing.

The parallel layout cannot feed a shifted immediate operand directly into its address-producing ALU in the same pass. The serial layout can. The actual immediate operand width and permitted shift encodings of a new instruction must be specified; the question does not fix them, so no particular enlarged instruction encoding is implied.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 3 / b / Solution by

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Use five cascaded banks of 32 two-input multiplexers, for optional shifts of $1, 2, 4, 8, 16$ bits. The original circuit schematic below shows one bank per shift-amount bit; this is a left bit shift with zero fill, not a bit rotation.

Figure 1.
Five optional power-of-two shifts implement every 32-bit logical left-shift distance
. **Details**.

s = \sum_{j = 0}^{4} s_{j} 2^{j}

, stage

j

selects either its unchanged input or that input shifted left by

2^{j}

. For bit position

i

, the shifted candidate comes from position

i - 2^{j}

when it exists, and otherwise from zero. Composing the chosen stages shifts by the sum of their distances, so each amount from

0

31

is represented exactly by its five binary control bits. There are

5 \times 32 = 160

one-bit multiplexers, with five multiplexer delays along a bit path.

A one-bit multiplexer with selector

s

, unselected input

u

and selected input

v

has output $(\neg s \land u) \lor (s \land v)$ . It can be made from one NOT gate, two AND gates and an OR gate; a bank can share the selector inversion. The two possible selector values directly verify its behaviour.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 3 / a / Solution by

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The following original schematic shows the two data organisations. Register-address, write-enable and memory controls are common background; the diagram highlights the changed combinational logic paths.

Figure 1.
Parallel ALU/shifter selection versus a shifter feeding one ALU operand
. **Details**.

In the parallel design the result-source multiplexer selects either the arithmetic logic unit or barrel shifter. Its control is additional to the ALU function and shift amount. (i) Addition: read the two operands, select ALU addition and select the ALU result; the shift amount is irrelevant. (ii) Constant left bit shift: read the operand to be shifted, set the shift amount from the immediate operand and select the barrel shifter result; the ALU operation is irrelevant.

In the serial design the result comes through the ALU, so that result-source selection disappears. Its shift-amount control is now relevant to arithmetic as well. (i) Addition: set the barrel shifter to zero shift and select ALU addition, so its inputs are the unshifted processor register values. (ii) Constant left bit shift: set the requested shift and select an ALU operation that passes the shifted operand through. If the ALU lacks that operation, implement it or provide a selectable zero on its other input and add zero. This requirement should be stated, rather than assuming that an ordinary two-input add automatically performs a shift alone.

The ALU result can still supply the memory address. For a register-result instruction, enable processor register writeback and leave memory writes disabled. If the ISA requires shift carry flags, the flag-generation control must retain the barrel shifter's outgoing-bit information; blindly using a pass-through ALU's arithmetic carry is insufficient.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 2 / b / Solution by

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Maintain a counter and independent timed finite-state machine for each detector–light pair, while sharing the interrupt scan and timer infrastructure. Blocking for one channel's flash would unnecessarily delay every other channel.

eye_handler():
    for i in all_channels:
        if EYE_DETECTED[i] != 0:
            EYE_DETECTED[i] = 0
            pending[i] = pending[i] + 1

main_event_loop():
    initialise each LIGHT[i] = 0
    initialise pending[i] = 0, state[i] = IDLE
    enable detector interrupts
    forever:
        now = monotonic_timer_snapshot()
        for i in all_channels:
            service_channel(i, now)
        arrange the next wake-up for new work or the earliest deadline

service_channel is the three-state sequencer from (a), with its own started[i] and an interrupt-safe try_take_event(i). Shared interrupt demultiplexing uses separate if tests, not an else if chain: simultaneous pending detectors must all be acknowledged and counted. If a new detector becomes pending during the scan, the controller must retrigger while a flag remains set or the handler must rescan appropriately; the exact interrupt controller semantics must be checked rather than assuming a single scan can never miss an edge.

One hardware timer can schedule the earliest active channel deadline. On its expiry, service every due channel and rearm for the next deadline; a periodic tick with adequate resolution is a simpler alternative. Detectors and the timer can then interleave without serial one-second waits. The handler/main-program counter accesses need the same short critical section protection as in (a). Keep timing state in one execution context, or protect it too if both a timer handler and the main program modify it.

The loop invariants are per channel: the pending count equals recorded but unstarted events, ON means that channel's light is on, and GAP prevents a new flash until one second after its preceding light-off transition. Different channels may flash simultaneously. The event latch rearming limitation, finite backlog capacity and timer-resolution qualifications apply independently to each channel. These cannot be solved by replacing several event counters with one global Boolean variable.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 2 / a / Solution by

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A short interrupt handler should acknowledge the detector and count work; a timed finite-state machine should generate the flashes. A Boolean “someone arrived” variable cannot preserve several queued detections. This is an interrupt-driven pulse sequencer. Initialise the light off, the pending-event counter to zero and the sequencer to IDLE before enabling interrupts.

In the following pseudocode, interrupt acknowledgement uses the source-specified operation of writing zero. The atomic operation and timer calls name abstract services, not undocumented device registers of a particular microcontroller.

eye_handler():
    if EYE_DETECTED != 0:
        EYE_DETECTED = 0
        pending = pending + 1

try_take_event():
    briefly mask the detector interrupt
    if pending == 0: taken = false
    else: pending = pending - 1; taken = true
    restore the previous interrupt mask
    return taken

service(now):
    if state == ON and elapsed(now, started) >= one_second:
        LIGHT = 0
        state = GAP
        started = now
    if state == GAP and elapsed(now, started) >= one_second:
        state = IDLE
    if state == IDLE and try_take_event():
        LIGHT = 1
        state = ON
        started = now

The main program repeatedly handles a new event or the next timer deadline and calls service. The ON state lasts one second; every completed flash enters GAP, even if the queue is empty at that instant. An arrival during that gap must wait for it to expire. Otherwise turning the light off and immediately treating the device as idle could allow a new flash too soon. Once a gap has expired, a queued event starts a new flash; if no work is pending the device remains idle. Removing a pending event only when a flash starts gives one completed flash per consumed event.

An interrupt can arrive during the main program's decrement. Without a critical section, its increment can be overwritten by a race condition. Merely declaring the counter volatile, as in volatile-qualified objects in C, does not make the decrement an atomic operation. Short interrupt masking, or an appropriate atomic operation, protects it; interrupts must remain enabled during the one-second intervals so that detections continue to be recorded.

A calibrated busy-wait loop is simple, but occupies the CPU and its duration depends on instruction timing, compiler transformations and time spent in interrupts. Polling a hardware timer avoids calibration dependence but still consumes CPU while polling. A timer interrupt or timer comparison deadline permits useful work or safe sleeping between transitions and is preferable for precise timing. If sleeping, the test for queued work and entry into sleep must avoid a lost wake-up. By the modulo-counter elapsed-time identity, a wrapping digital counter is usable if elapsed-time subtraction is unsigned and the real observation interval is less than its modulus; a wide enough counter or suitable bounded intervals make this explicit. Software dispatch adds bounded latency, so the specification is achieved to timer/interrupt-service resolution; stricter physical pulse-width requirements call for hardware output comparison or a suitably prioritised timer handler.

Finally, the device register is only a single-bit event latch. Two physical detections before acknowledgement may coalesce, so no software can recover their multiplicity from that bit alone. The event counter must also have enough capacity for the allowed backlog; indefinitely many arrivals faster than one flash every two seconds cannot be guaranteed with finite storage. These are explicit hardware/rate assumptions, not missing input files. Keeping the handler short minimises the rearming interval but cannot abolish those limitations.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 1 / e / Solution by

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Use four working processor registers by packing the growing quotient into the vacated low bits of the shifting dividend. The following is A32 assembly language with conditional execution, an allowed instance of the question's general 32-bit Reduced instruction set computer. It is not restricted to the sixteen-bit encodings in the supplied Thumb instruction set table. On entry r0 is the dividend and r1 the positive divisor; r2 becomes the high remainder machine word and r3 counts iterations. The quotient is returned in r0 and the ordinary remainder remains in r2.

mov   r2, #0
mov   r3, #32
loop:
adds  r0, r0, r0
adcs  r2, r2, r2
cmp   r2, r1
subcs r2, r2, r1
adc   r0, r0, #0
subs  r3, r3, #1
bne   loop
bx    lr

Here subcs means conditional sub when arithmetic carry is set, without the flag-setting suffix. adc also preserves flags. Consequently the arithmetic carry from cmp survives until it is inserted as the next quotient bit. The loop has seven instructions, one of them conditional, and no data-dependent branch. Its sole branch is the backwards loop branch, taken 31 times. It uses no separate quotient processor register, zero processor register, temporary comparison processor register or saved arithmetic carry processor register. A Thumb instruction set rendering using conditional execution would need an explicit conditional-execution encoding such as it cs; that is an additional encoded instruction, not an unexplained free operation.

The packed restoring division loop invariant relates it to the displayed algorithm. Specifically, let

M = 2^{32}

, let

a

retain its original mathematical value, and let

k

be the number of completed iterations. Define the processed prefix

p_{k} = ⌊ a / 2^{32 - k} ⌋

, its quotient

Q_{k} = ⌊ p_{k} / b ⌋

and remainder

R_{k} = p_{k} - b Q_{k}

. The processor register loop invariant is

high = R_{k}, low = (a 2^{k} mod M) + Q_{k}, 0 \leq Q_{k} < 2^{k} .

(1)

The two terms in the low machine word occupy disjoint bit positions. Its next outgoing arithmetic carry is therefore the next original dividend bit, not a quotient bit. adds shifts the low machine word; adcs doubles the high remainder and incorporates that dividend bit. cmp decides whether this trial remainder is at least the divisor; subcs performs the conditional subtraction, and adc appends its decision to the shifted quotient. This is exactly the doubling, compare/subtract and quotient-bit update, with the counter maintained separately. Before processing bit

k \leq 32

, the trial remainder is at most

p_{k} < 2^{k} \leq M

, so the high-word addition does not require a hidden 33rd remainder bit for this 32-bit dividend problem. After 32 iterations the residual dividend portion is zero, giving the stated outputs.

There is a printed source error in the auxiliary bound. At the initial state, choosing valid inputs

a = b = 1

makes the printed strict inequality

r 2^{j} < b 2^{32}

false. The algorithm instead preserves

0 \leq r < b 2^{32}

for its unpacked 64-bit variable, together with its printed equality loop invariant. Doubling and subtracting

b 2^{32}

when necessary preserves that corrected bound. At termination the equality becomes

a 2^{32} = q b 2^{32} + r

; since

r

is then divisible by

2^{32}

, it gives

0 \leq a - q b < b

. This source error does not invalidate the algorithm or the packed implementation. The figure is mathematical pseudocode: its 2^32 denotes exponentiation, rather than C's XOR operator.

The displayed A32 routine assembled successfully with Clang and was disassembled to check the conditional and non-flag-setting forms. Its carry flag model was checked exhaustively at an eight-bit machine word size and against boundary and randomized 32-bit divisions. No native ARM architecture family execution is claimed.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 1 / d / Solution by

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A subtract with carry instruction consumes the no-borrow carry flag. Its arithmetic is $Z = X - Y - (1 - C_{in}) (mod 2^{32})$ . Hence a low-limb subs followed immediately by a high-limb sbcs propagates exactly the low subtraction's borrow.

For example, with the same limb assignment as in (c):

subs r0, r0, r2
sbcs r1, r1, r3

It uses an ordinary 32-bit adder by complementing every bit of the subtrahend and adding the incoming arithmetic carry. For

M = 2^{32}

, the unreduced adder sum is

X + (M - 1 - Y) + C_{in} .

(1)

If this is

Z + M C_{out}

, rearrangement gives

X - Y - (1 - C_{in}) = Z - M (1 - C_{out})

. Thus both the result and outgoing no-borrow flag have the required meanings. With incoming arithmetic carry one this becomes ordinary subtraction.^[ref]

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 1 / c / Solution by

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Let r1:r0 hold the first operand, high limb first, and r3:r2 the second. In assembly language the addition can be written:

adds r0, r0, r2
adcs r1, r1, r3

The first instruction produces the low result and its arithmetic carry; the second immediately consumes that arithmetic carry while adding the high limbs. No intervening flag-setting instruction is permitted.

For a proof, put

M = 2^{32}

and denote the input limbs by

X_{1}, X_{0}, Y_{1}, Y_{0}

. If the low addition gives

Z_{0}

and arithmetic carry

c

, then

X_{0} + Y_{0} = Z_{0} + M c

. The high addition gives

Z_{1}

and final arithmetic carry

d

, so

X_{1} + Y_{1} + c = Z_{1} + M d

. Multiplying the second identity by

M

and combining yields

(M X_{1} + X_{0}) + (M Y_{1} + Y_{0}) = M Z_{1} + Z_{0} + M^{2} d .

(1)

The processor register pair is the correct result modulo $2^{64}$ , and the final arithmetic carry records overflow beyond that unsigned width. If the mathematical sum fits in 64 bits, no reduction changes it.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 1 / b / Solution by

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Put

M = 2^{n}

for an

n

-bit processor register. The carry flag for addition satisfies $bin (x) + bin (y) = bin (z) + MC$ : the result retains the low

n

bits and

C = 1

records an arithmetic carry beyond them.

For the ARM architecture family subtraction convention, $bin (x) - bin (y) = bin (z) - M (1 - C)$ . Thus

C = 1

means no borrow, equivalently the unsigned minuend is at least the subtrahend. This flag is different from signed overflow: an arithmetic carry decision is not a test of the signed result.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof / 1 / a / Solution by

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Write the bit vector as

a = (a_{n - 1}, \dots, a_{0})

, with

a_{0}

the least significant bit. Its unsigned interpretation of a bit string is $bin (a) = \sum_{i = 0}^{n - 1} a_{i} 2^{i}$ , where each

a_{i} \in {0, 1}

. The range is the integers from

0

through

2^{n} - 1

; a leading one contributes positive weight

2^{n - 1}

, not a sign.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof resit / 8 / d / Solution by

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Let

K

abbreviate

Q (c_{1}) \lor Q (c_{2})

, and group the three equality alternatives on the left. The proof uses the binary disjunction elimination rule twice, so no unproved three-way derived rule is needed.

Line	Formula	Justification
1	$\forall x ((x = c_{0} \lor x = c_{1}) \lor x = c_{2})$	Premise
2	$\neg Q (c_{0})$	Assume for the first implication
3	$\exists x Q (x)$	Assume for the second implication
4	$Q (u)$	Assume with fresh witness name $u$
5	$(u = c_{0} \lor u = c_{1}) \lor u = c_{2}$	Universal quantifier elimination rule, 1
6	$u = c_{0} \lor u = c_{1}$	Assume the first outer case
7	$u = c_{0}$	Assume the first inner case
8	$Q (c_{0})$	Equality elimination rule, 7 and 4
9	$⊥$	Negation elimination rule, 2 and 8
10	$K$	Logical falsity elimination rule, 9
11	$u = c_{1}$	Assume the second inner case
12	$Q (c_{1})$	Equality elimination rule, 11 and 4
13	$K$	Disjunction introduction rule, left, 12
14	$K$	Disjunction elimination rule, 6, 7–10 and 11–13
15	$u = c_{2}$	Assume the second outer case
16	$Q (c_{2})$	Equality elimination rule, 15 and 4
17	$K$	Disjunction introduction rule, right, 16
18	$K$	Disjunction elimination rule, 5, 6–14 and 15–17
19	$K$	Existential quantifier elimination rule, 3 and 4–18
20	$(\exists x Q (x)) \to K$	Implication introduction rule, discharging 3–19
21	$\neg Q (c_{0}) \to (\exists x Q (x)) \to K$	Implication introduction rule, discharging 2–20

The witness name is absent from

K

and from every assumption remaining after line 19, so the existential elimination is legal. Each equality is used in the forward direction supplied by the printed equality rule. The three named constants need not denote distinct objects: the case proof requires only that they exhaust the domain. This is existential quantification over a finitely named domain followed by exclusion of the first case.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof resit / 8 / c / Solution by

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For readability write

R (s, t)

for the uninterpreted relation

s ∋ t

. In the first proof, introduce the universal quantifier inside the existential witness scope:

Line	Formula	Justification
1	$\exists y \forall x R (x, y)$	Premise
2	$\forall x R (x, w)$	Assume with fresh witness name $w$
3	$R (u, w)$	Universal quantifier elimination rule, 2; choose fresh arbitrary $u$
4	$\exists y R (u, y)$	Existential quantifier introduction rule, 3
5	$\forall x \exists y R (x, y)$	Universal quantifier introduction rule, 4; $u$ is absent from open assumptions
6	$\forall x \exists y R (x, y)$	Existential quantifier elimination rule, 1 and 2–5

In the second proof, first close the witness scope and then generalize the arbitrary object:

Line	Formula	Justification
1	$\exists y \forall x R (x, y)$	Premise; choose $u$ arbitrary and fresh for this premise
2	$\forall x R (x, w)$	Assume with fresh $w$ , also different from $u$
3	$R (u, w)$	Universal quantifier elimination rule, 2
4	$\exists y R (u, y)$	Existential quantifier introduction rule, 3
5	$\exists y R (u, y)$	Existential quantifier elimination rule, 1 and 2–4
6	$\forall x \exists y R (x, y)$	Universal quantifier introduction rule, 5

These are distinct proof trees: the final two rule applications are interchanged, and their freshness conditions have been checked in their respective contexts. They express the quantifier order and uniform witness principle: a single witness working for every object also supplies a witness for each object individually.

The converse is not valid. In a domain

{0, 1}

interpret

R (s, t)

as equality of its arguments. Every object has a witness, namely itself, but no one object equals both 0 and 1. The premise of the converse is true and its conclusion false. The symbol

∋

is an arbitrary binary relation here; no set-membership axioms may be imposed on it without an additional premise.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof resit / 8 / b / Solution by

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The displayed derivation is invalid, although its final conjecture is valid. Its existential-elimination step exports

T (x_{0})

with the local witness name still free, violating the eigenvariable condition. Introducing an existential quantifier afterwards does not repair that earlier invalid rule application.

Move the existential quantifier introduction rule inside the witness scope:

Line	Formula	Justification
1	$\forall x (S (x) \to T (x))$	Premise
2	$\exists x S (x)$	Premise
3	$S (u)$	Assume with fresh $u$
4	$S (u) \to T (u)$	Universal quantifier elimination rule, 1
5	$T (u)$	Implication elimination rule, 3 and 4
6	$\exists x T (x)$	Existential quantifier introduction rule, 5
7	$\exists x T (x)$	Existential quantifier elimination rule, 2 and 3–6

The exported formula contains no free

u

, and neither original premise contains that name. The witness assumption is now discharged legally.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof resit / 8 / a / Solution by

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In a finite domain

{d_{1}, \dots, d_{n}}

, a true existential premise says that at least one

d_{j}

satisfies

ϕ

. The subproof treats its witness as an unknown object named

v

, derives

κ

without relying on which object was chosen, and can therefore be applied to the actual witness. Thus

κ

follows whenever the existential premise is true. This argument does not require knowing the domain's size or selecting a particular named element in advance.

The existential quantifier elimination rule in sequent form records the same assumption discharge: a derivation of

Γ, ϕ (v) ⊢ κ

yields

Γ, \exists x ϕ (x) ⊢ κ

. The natural-deduction box represents the temporary witness assumption that the sequent rule replaces by the existential premise.

The eigenvariable condition requires that

v

have no free occurrence in the other undischarged assumptions, the existential premise or the exported conclusion

κ

. Bound occurrences can be renamed harmlessly. This freshness condition keeps

v

from denoting a previously special object and prevents witness escape. Without it, one could export

S (v)

from

\exists x S (x)

, falsely asserting that an arbitrarily named object has the witness property. A two-element domain with only one element satisfying

S

supplies an immediate counterexample.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof resit / 7 / e / Solution by

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Write

H

for

(ϕ \to ψ) \to ϕ

. The following derives Peirce's law directly from the printed primitive rules, including double-negation elimination:

Line	Formula	Justification
1	$H$	Assume for the final implication
2	$\neg ϕ$	Assume locally
3	$ϕ$	Assume inside the scope of 2
4	$⊥$	Negation elimination rule, 2 and 3
5	$ψ$	Logical falsity elimination rule, 4
6	$ϕ \to ψ$	Implication introduction rule, discharging 3–5
7	$ϕ$	Implication elimination rule, 1 and 6
8	$⊥$	Negation elimination rule, 2 and 7
9	$\neg\neg ϕ$	Negation introduction rule, discharging 2–8
10	$ϕ$	Double-negation elimination, 9
11	$((ϕ \to ψ) \to ϕ) \to ϕ$	Implication introduction rule, discharging 1–10

Every assumption is discharged, so the last formula is a theorem. In particular, no unproved appeal to the derived RAA rule is hidden in the argument.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof resit / 7 / d / Solution by

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The supplied double-negation elimination rule provides the classical step needed to recover each positive component:

Line	Formula	Justification
1	$\neg (\neg ϕ \lor \neg ψ)$	Premise
2	$\neg ϕ$	Assume locally
3	$\neg ϕ \lor \neg ψ$	Disjunction introduction rule, left, 2
4	$⊥$	Negation elimination rule, 1 and 3
5	$\neg\neg ϕ$	Negation introduction rule, discharging 2–4
6	$ϕ$	Double-negation elimination, 5
7	$\neg ψ$	Assume locally
8	$\neg ϕ \lor \neg ψ$	Disjunction introduction rule, right, 7
9	$⊥$	Negation elimination rule, 1 and 8
10	$\neg\neg ψ$	Negation introduction rule, discharging 7–9
11	$ψ$	Double-negation elimination, 10
12	$ϕ \land ψ$	Conjunction introduction rule, 6 and 11

Both local negated assumptions have been discharged. The proof establishes the positive conjunction without assuming an unproved derived version of De Morgan's laws.

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 Pinned article: Introduction to the OurBigBook Project

Welcome to the OurBigBook Project! Our goal is to create the perfect publishing platform for STEM subjects, and get university-level students to write the best free STEM tutorials ever.

Everyone is welcome to create an account and play with the site: ourbigbook.com/go/register. We belive that students themselves can write amazing tutorials, but teachers are welcome too. You can write about anything you want, it doesn't have to be STEM or even educational. Silly test content is very welcome and you won't be penalized in any way. Just keep it legal!

Video 1.

Intro to OurBigBook

. Source.

We have two killer features:

topics: topics group articles by different users with the same title, e.g. here is the topic for the "Fundamental Theorem of Calculus" ourbigbook.com/go/topic/fundamental-theorem-of-calculus
Articles of different users are sorted by upvote within each article page. This feature is a bit like:
- a Wikipedia where each user can have their own version of each article
- a Q&A website like Stack Overflow, where multiple people can give their views on a given topic, and the best ones are sorted by upvote. Except you don't need to wait for someone to ask first, and any topic goes, no matter how narrow or broad
This feature makes it possible for readers to find better explanations of any topic created by other writers. And it allows writers to create an explanation in a place that readers might actually find it.
Figure 1.
Screenshot of the "Derivative" topic page
. View it live at: ourbigbook.com/go/topic/derivative
Video 2.
OurBigBook Web topics demo
. Source.
local editing: you can store all your personal knowledge base content locally in a plaintext markup format that can be edited locally and published either:
- to OurBigBook.com to get awesome multi-user features like topics and likes
- as HTML files to a static website, which you can host yourself for free on many external providers like GitHub Pages, and remain in full control
This way you can be sure that even if OurBigBook.com were to go down one day (which we have no plans to do as it is quite cheap to host!), your content will still be perfectly readable as a static site.
Figure 2.
You can publish local OurBigBook lightweight markup files to either OurBigBook.com or as a static website
.
Figure 3.
Visual Studio Code extension installation
.
Figure 4.
Visual Studio Code extension tree navigation
.
Figure 5.
Web editor
. You can also edit articles on the Web editor without installing anything locally.
Video 3.
Edit locally and publish demo
. Source. This shows editing OurBigBook Markup and publishing it using the Visual Studio Code extension.
Video 4.
OurBigBook Visual Studio Code extension editing and navigation demo
. Source.
Internal cross file references done right:
Infinitely deep tables of contents:
Figure 6.
Dynamic article tree with infinitely deep table of contents
.
Live URL: ourbigbook.com/cirosantilli/chordate
Descendant pages can also show up as toplevel e.g.: ourbigbook.com/cirosantilli/chordate-subclade

All our software is open source and hosted at: github.com/ourbigbook/ourbigbook

Further documentation can be found at: docs.ourbigbook.com

Feel free to reach our to us for any help or suggestions: docs.ourbigbook.com/#contact

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