A sequential circuit has stored state. Its future output can therefore depend on earlier inputs as well as the present inputs.
An electronic display cycling through the six die faces while a switch is pressed. A modulo-six counter and combinational logic can drive seven lights arranged as die pips. The apparent unpredictability comes from uncertainty in release timing relative to a rapid clock signal; deterministic cycling alone does not establish equal outcome probabilities.
A fixed-width collection of flip-flops storing a binary representation. A synchronous load-enabled digital register captures all its input bits on the active clock edge when load is asserted and otherwise retains its old value. One multiplexer before each D flip-flop can select new data or feedback from its old output. A processor register is a particular use inside a processor; temporary state in a standalone binary multiplier is another.
A chain of digital registers that transfers each stored value to the next stage at a clock edge. A serial-in parallel-out shift register exposes the stored history simultaneously. With the current input and delayed samples, combinational logic can evaluate a function of the latest samples.
A shift register accepting one sample at each clock edge and exposing every stored stage as a parallel output.
A directed graph with one vertex for each state and labelled edges for the permitted transitions. A finite counter has a directed cycle when every state has one successor.
A counter stores a binary representation of a state, usually advancing by one increment or decrement modulo when it has bits.
A digital counter cycling through six stored values. With ordinary binary representation, the valid three-bit states are . The unused encodings require either an initialization assumption or specified recovery transitions.
A cascade in which an output transition of one flip-flop clocks the next. With positive-edge-triggered toggle stages and uncomplemented connections, it decrements modulo : a zero bit rises to one and propagates a borrow, while a one bit falls to zero and stops propagation. Ripple propagation takes time, so intermediate transient states are not the settled counter state.
A flip-flop stores one bit and updates it at a specified clock edge; an asynchronous clear can override that clocked update. Signal polarity is part of the specification, not something inferred from the name alone.
The time from a triggering clock edge to the corresponding settled output of a flip-flop, under specified loading. The time available between successive active clock edges must accommodate this delay, the combinational critical path, the receiving flip-flop's setup time, and any clock uncertainty.
The data input must remain stable for a specified interval before the sampling clock edge and a specified interval after it. Violations can prevent a well-defined sampled bit.
The minimum interval after an active clock edge during which the data input of a flip-flop must remain stable for specified operation. It constrains how quickly a newly launched value may reach the receiving flip-flop.
The minimum interval before an active clock edge during which the data input of a flip-flop must remain stable for specified operation. It constrains the latest arrival of new data at the receiving flip-flop.
A control that resets stored state independently of the clock edge. An active-low clear is asserted by a low signal; clocked sampling resumes after the clear is released.
At the active clock edge, . An asynchronous clear, when provided and asserted, takes precedence over this data-sampling rule.
At the active clock edge, the next state is : inputs hold, reset, set, and toggle. In particular, gives , whereas gives . The standard function table is illustrated by a positive-edge device in the [ref]. Its asynchronous reset is active high; another circuit may specify an active-low clear.
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Sequential logic is a type of digital logic circuit whose output depends not only on the current inputs but also on the history of past inputs. This means that the output state of a sequential logic circuit can change based on a sequence of inputs and the current state of the system. Unlike combinational logic, where the outputs are determined solely by the present inputs, sequential logic incorporates storage elements (memory), allowing it to maintain a state over time.