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An analog-to-digital converter produces a discrete numerical code from an input voltage. Its specifications include input range, resolution, conversion rate, input impedance, offset, gain error and nonlinearity. A uniform $b$-bit converter covering voltage span $V_{\mathrm{span}}$ has nominal spacing $q\simeq V_{\mathrm{span}}/2^b$. The uniform-quantization error bound applies to rounding inside the range, while clipping is a different error. Sampling and quantization are separate operations: neither sufficient sampling rate nor a large bit count alone guarantees accurate reconstruction.

The voltage-to-current ratio of a selected Bloch eigenmode at a specified position within a periodic cell. It depends on the chosen cell boundary, unlike the cell's propagation eigenvalues. In a pass band a physical semi-infinite mode carries positive real power; in an ideal stop band its input impedance is reactive and the mode decays into the line.

The capacitive bridging complex-error bandwidth is the largest frequency over which a receiving port preserves the source phasor within a specified complex relative gain error. The criterion includes phase shift as well as amplitude. A large DC input impedance alone cannot establish this bandwidth when input capacitance matters. The manufacturer's input models explicitly include resistive and capacitive paths.^[ref]

For the scalar impedance bridging with capacitive input model, assume a positive real source electrical resistance $R_s$, receiver resistance $R_{\mathrm{in}}>0$, and input capacitance $C_{\mathrm{in}}>0$ in parallel. Let $V_s$ be the unloaded source phasor. A voltage divider givesFor tolerance $0<\eta <1$, the complex relative gain error isIts square is strictly increasing in $x^2$, since its derivative is $(1+2g)/[(1+g{)}^2+x^2{]}^2>0$. Thus satisfying $E(f)\le \eta$ defines a continuous frequency interval starting at DC, whenever it is feasible. Rearranging givesThe DC error floor is ${\eta }_0=g/(1+g)$. If $\eta <{\eta }_0$, no frequency meets the tolerance; if $\eta ={\eta }_0$, only DC does. The boxed positive bandwidth applies when $\eta >{\eta }_0$.

For an original near-limit example, choose $R_s=10\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$ and $C_{\mathrm{in}}=100\mathrm{pF}$. Then $g=0.01$ and the DC error is about 0.9901 percent. A 1 percent full-complex tolerance leaves onlyAn amplitude-only 1 percent criterion, $|H|\ge 0.99$, instead allows about $2273.47\mathrm{Hz}$. The half-power (approximately $-3\mathrm{dB}$) signal bandwidth, relative to DC, is $(1+g)/(2\pi R_s{C}_{\mathrm{in}})\approx 160.75\mathrm{kHz}$. These are three distinct specifications of this same ideal model.

The square-root collapse of capacitive bridging bandwidth near the DC error floor follows by factoring the numerator:For fixed $g>0$ and $\eta \downarrow {\eta }_0$,This asymptotic equivalence explains the sharp loss of usable bandwidth when the resistive divider has already consumed nearly all the error allowance. Increasing $R_{\mathrm{in}}$ or reducing $R_s$ changes that floor; reducing only $C_{\mathrm{in}}$ rescales a feasible bandwidth but cannot remove infeasibility at DC.

The criterion also controls a complete waveform. Suppose a source waveform $v_s$ is both a square-integrable function and a bandlimited function, with spectrum supported where $|H-1|\le \eta$. For the corresponding zero-state response $v_L$, the Fourier transform of $v_L-v_s$ is $(H-1){\hat{v}}_s$. The Plancherel theorem, or the norm bound for a Fourier multiplier on L2, givesHere the Fourier transform uses the frequency-in-hertz convention, so the displayed Plancherel theorem has no extra normalization factor. This bound includes waveform changes caused by phase. It applies to the zero-state response of the stated frequency response. Any additional homogeneous solution from initially stored energy contributes its own error.

A bench check therefore needs both amplitude ratio and phase shift, with probe and cable capacitance included in the port model. Magnitude-only observations determine $|H|$ without determining $|1-H|$. The formula describes this chosen passive input network; additional amplifier dynamics require their own transfer function.

For an ideal capacitor in series with a parallel resistor and inductor, $Z=1/(i\omega C)+(R\parallel i\omega L)$. A finite positive frequency with real input impedance exists precisely when $R^{2}C>L$. At that frequency ${\omega }_{\ast }=[LC-L^2/R^2{]}^{-1/2}$ and $Z_{\ast }=L/(RC)$. The resistor's voltage can exceed the source voltage because the reactive voltage drops cancel in the series sum; all average dissipation is still supplied by the source.

Consider an op amp integrator with infinite input impedance, an internal controlled voltage $u=-A(s)v$ where $v$ is the inverting-input voltage, and a series output impedance equal to a resistance $r_o$. Assume no external output load. Writing $y$ for the output, Kirchhoff's current law givesEliminating $u$ and $v$ yieldsThe expression at $r_o=0$ is obtained by its limit. In particular, constant gain $A_0$ and $r_o=0$ give $H(s)=-A_0/[1+sRC(1+A_0)]$: a finite direct-current gain followed by an integrating regime. For the dominant-pole model $A(s)=A_0/(1+s/{\omega }_a)$ and $r_o=0$,If $A_0\gg 1$ and $A_0{\omega }_{a}RC\gg 1$, there are separated turnover frequencies near $1/(A_{0}RC)$ and $A_0{\omega }_a$. The gain magnitude is respectively constant, proportional to ${\omega }^{-1}$ and proportional to ${\omega }^{-2}$. With the convention $e^{i\omega t}$ a continuous phase choice passes from $180^{\circ }$ through $90^{\circ }$ to $0^{\circ }$. If $r_o>0$ and $A(i\omega )\to 0$, capacitive feedthrough instead gives the ultimate limit $r_o/(R+r_o)$. Specifying finite gain alone therefore does not specify a unique high-frequency response.

With the noninverting input grounded, a differential input impedance $R_{\mathrm{in}}$ draws current from the summing node. For zero output impedance, $V_o=-Av$ and Kirchhoff's current law gives $(v-V_i)/R_1+(v-V_o)/R_2+v/R_{\mathrm{in}}=0$. Eliminating $v$ yields the displayed voltage gain. The resistor-ratio result requires $|A|\gg 1+R_2/R_1+R_2/R_{\mathrm{in}}$ as well as stable, unsaturated operation. The same expression applies to small-signal phasors with complex $A(f)$.

An ideal operational amplifier has infinite open-loop gain and input impedance, zero output impedance, unlimited response speed and zero input offset voltage and input bias current. Its input currents vanish. In a stable linear circuit with negative feedback and a finite output, its differential input voltage tends to zero as the open-loop gain tends to infinity. Thus $i_{+}=i_{-}=0$ and $v_{+}=v_{-}$ are the familiar conditional circuit rules. The equality of the input voltages cannot be imposed on an open-loop, unstable or saturated circuit.

Impedance bridging, also called voltage bridging, connects a source to a much higher load impedance so that little signal electric potential difference is lost across the source's output impedance. It is useful when the receiver should observe a signal while drawing little electric current from its source.

Represent a linear source at one frequency by open-circuit phasor $V_s$ and series electrical impedance $Z_s$. With receiving input impedance $Z_L$, the voltage divider givesThus $|Z_s/Z_L|\ll 1$ makes $H$ close to one as a complex number, controlling both amplitude and phase loading. For positive electrical resistances, the relative voltage loss is $R_s/(R_s+R_L)$. A $1\mathrm{k\Omega }$ source feeding $99\mathrm{k\Omega }$ retains $99\%$ of its open-circuit voltage; feeding $9\mathrm{k\Omega }$ retains $90\%$.

For a tolerance $\eta$ on that resistive relative loss,The often convenient ten-to-one ratio is therefore a chosen accuracy compromise, not a universal definition. A one-percent limit requires at least a ninety-nine-to-one ratio in this ideal resistive model. Voltage divider loading error gives the related loading problem when the source is itself a divider.

Impedance bridging with capacitive input explains why a large DC electrical resistance is not enough at every frequency. With source resistance $R_s$ and receiving $R_{\mathrm{in}}$ in parallel with capacitance $C_{\mathrm{in}}$,At $R_s=1\mathrm{k\Omega }$ and $R_{\mathrm{in}}=1\mathrm{M\Omega }$, the DC ratio is about $0.999$. With $C_{\mathrm{in}}=100\mathrm{pF}$, its magnitude at $1\mathrm{MHz}$ is only about $0.846$. The capacitive path loads the source despite the high DC input resistance.

Texas Instruments' three-amplifier presentation motivates high-input-impedance buffering by explicitly showing that source current and nonzero source output impedance degrade accuracy.^[ref] A buffer changes the load seen by the signal source; its own finite input and output behavior still matter.

Impedance matching has a different objective in maximum-power-transfer applications. For a resistive source, choosing equal source and load resistances gives half the open-circuit voltage, whereas bridging seeks a ratio near one. Signal fidelity, delivered power and high-frequency transmission behavior require their appropriate models.

Impedance bridging with capacitive input treats a receiver's input as a resistance in parallel with a capacitance. Even when its DC input impedance is large, the capacitive path can draw appreciable electric current at higher frequency, changing both the amplitude and phase of the observed electric potential difference.

For source resistance $R_s$, receiving resistance $R_{\mathrm{in}}$ and input capacitance $C_{\mathrm{in}}$, use sinusoidal steady-state phasors and a linear source model. The receiving electrical admittance is $1/R_{\mathrm{in}}+\mathrm{i}\omega C_{\mathrm{in}}$, soHere $V_s$ is the open-circuit source phasor; $V_L$ is the loaded terminal phasor. The impedance bridging objective is $H$ near one, rather than merely a large quoted DC input resistance.

The amplitude and phase responses areAn amplitude-only tolerance and a tolerance on the full complex number express different requirements. The latter measuresFor positive resistances, capacitance and a chosen $0<\eta <1$, the capacitive bridging complex-error bandwidth condition $|1-H|\le \eta$ requiresA negative numerator means even the DC loading error exceeds the tolerance.

In an original example, $R_s=1\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$ and $C_{\mathrm{in}}=100\mathrm{pF}$ give $g=0.001$. A one-percent complex-error tolerance permits frequencies only up to about $15.9\mathrm{kHz}$. At $100\mathrm{kHz}$ the amplitude ratio remains about $0.997$, but the phase is about $-3.59^{\circ }$ and the complex error about $0.0627$. A small amplitude error can coexist with a materially larger waveform-phase error.

High-input-impedance buffers are motivated by just this source-loading problem. Texas Instruments' three-amplifier presentation shows how current drawn from a source with finite output impedance degrades accuracy and how input buffers reduce loading.^[ref] The chosen component values above are not specifications of a particular amplifier. A real receiver may require additional input paths, frequency-dependent source impedance and a model of the connected cable or probe.

A voltage gain determines a power gain only when the electrical conditions at both ports are included. The familiar equality between $20{\log }_{10}|A_v|$ and $10{\log }_{10}{G}_P$ requires a particular impedance relation; it is not a conversion between arbitrary voltage and power ratios.

Use phasors whose moduli are root mean square amplitudes, at one sinusoidal frequency. At a load with electrical impedance $Z$ and electrical admittance $Y=1/Z$, the current is $I=YV$. Its complex electrical power is $V{I}^{\ast }$, with the complex conjugate arising from the relative phase of the two sinusoids. Averaging $v(t)i(t)$ over a cycle gives the active powerTo see the averaging step, write $v(t)=\sqrt{2}|V|\cos (\omega t+{\varphi }_V)$ and similarly for $i(t)$. The product's cycle average is $|V||I|\cos ({\varphi }_V-{\varphi }_I)$, the real part of $V{I}^{\ast }$. Peak-amplitude phasors instead require an extra factor $1/2$.

Let $Y_{\mathrm{in}}$ describe the actual input impedance and $Y_L$ the actual load impedance. Take $\mathrm{Re}{Y}_{\mathrm{in}}>0$ and $\mathrm{Re}{Y}_L>0$ with nonzero terminal signals, and define currents into the amplifier at the input and into the load at the output. With the measured loaded voltage gain $A_v=V_L/V_{\mathrm{in}}$,Thus $G_P=|A_v{|}^2$ requires equality of the relevant electrical conductances, not merely equality of impedance moduli. For example, input $Z_{\mathrm{in}}=50\Omega$ and load $Z_L=(30+40i)\Omega$ both have modulus $50\Omega$, but their electrical admittances have real parts $0.020$ and $0.012\mathrm{S}$. The multiplier is $0.6$, so $G_P=0.6|A_v{|}^2$.

For real resistive ports this becomesTake an original example with measured $|A_v|=0.5$, $R_{\mathrm{in}}=10\mathrm{k\Omega }$ and $R_L=50\Omega$. The voltage gain is $-6.02\mathrm{dB}$, while the power gain is $50$, or $16.99\mathrm{dB}$. An active buffer can reduce the signal's electric potential difference while delivering more signal power than it accepts at its input; the supply provides the additional energy.

The amplifier's output impedance is distinct from the connected load impedance. To show why that distinction matters, model its output by a Thévenin equivalent with open-circuit voltage $A_0{V}_{\mathrm{in}}$ and series resistance $R_o$. The voltage divider givesWith $A_0=0.6$ and $R_o=10\Omega$, the $50\Omega$ load produces the preceding $A_v=0.5$ example. Differentiating $R_L/(R_o+R_L{)}^2$ gives $(R_o-R_L)/(R_o+R_L{)}^3$, so delivered power is largest at $R_L=R_o$, as in the maximum power transfer theorem. Here its power gain is $90$. Increasing $R_L$ much further makes $A_v$ approach $A_0$ but reduces delivered power. That high-load-impedance regime is impedance bridging, useful for sensing the source's voltage with little loading.

A bench demonstration uses a function generator, a known termination and an oscilloscope. The Keysight guide explains that an expected-load setting changes how amplitude is displayed for generators with a fixed series output impedance; a high-impedance load can receive twice the voltage expected for a matched $50\Omega$ termination.^[ref] As an independent low-frequency resistive calculation, an open-circuit source of $1\mathrm{V}$ root mean square with $50\Omega$ series resistance delivers $0.5\mathrm{V}$ and $5\mathrm{mW}$ to $50\Omega$. Into $1\mathrm{M\Omega }$ it delivers about $0.99995\mathrm{V}$ but only $1.00\mu \mathrm{W}$. The larger terminal reading accompanies much less delivered power. Specify the actual load, frequency and amplitude convention when comparing gain measurements.

Input capacitance describes the capacitive part of an electrical port's small-signal input impedance, under stated bias, frequency, and termination conditions. In a simple parallel model with the $e^{i\omega t}$ convention, its electrical admittance isThe electric current drawn by the capacitance grows with angular frequency even if the DC input resistance is enormous. Analog Devices distinguishes differential input paths from common-mode paths to ground: a quoted capacitance must identify which terminals are driven and how the remaining circuit is connected.^[ref]

For an original loading example, let $R_{\mathrm{in}}=10\mathrm{M\Omega }$ and $C_{\mathrm{in}}=20\mathrm{pF}$. At $10\mathrm{MHz}$, the capacitive reactance magnitude is only $1/(2\pi f{C}_{\mathrm{in}})\approx 796\Omega$. A source with electrical resistance $R_s=1\mathrm{k\Omega }$ therefore has loaded-to-unloaded phasor ratioThe DC ratio is about $0.99990$. Thus a resistance-only reading would miss a substantial high-frequency amplitude reduction. The numbers are chosen examples, not a specification for a named device.

For this same model, the source-to-input time constant is $(R_s\Vert R_{\mathrm{in}})C_{\mathrm{in}}$ and the DC-normalized half-power signal bandwidth is its reciprocal divided by $2\pi$. A complex-error requirement is instead governed by capacitive bridging complex-error bandwidth; these specifications answer different questions.

For input capacitance inferred from measured admittance, apply a small sinusoidal electric potential difference, measure the input electric current and its phase shift, and infer $\mathrm{Im}(I/V)/\omega$ within the parallel-capacitance approximation. Fixture, cable, and probe capacitances contribute to the measured port unless removed or included explicitly. Dependence on bias or frequency can make a single fitted $C_{\mathrm{in}}$ an inadequate model.

Input capacitance inferred from measured admittance is a parameter estimate from the quadrature component of a specified electrical port's response. In the parallel model of input capacitance, write its electrical admittance as $Y=G+i\omega C$ with the $e^{i\omega t}$ convention. A small sinusoidal excitation and simultaneous input-current measurement giveBoth amplitude ratio and relative wave phase matter. The differential versus common-mode terminals and operating point conditions must be specified, as in the manufacturer's input-path diagrams.^[ref]

For an original error calculation, suppose the amplitude ratio is exact but the measured current-to-voltage wave phase has offset $\delta$. Then $Y_{\mathrm{meas}}=Y{e}^{i\delta }$ andThe phase calibration error in an admittance-based capacitance estimate can therefore mix a conductance term into the small capacitive estimate. For small $\delta$, the leading error is $(G/\omega )\delta$, not a fixed percentage of $C$.

Choose $G=10\mu \mathrm{S}$, $C=20\mathrm{pF}$, and $f=10\mathrm{kHz}$. The true susceptance is only $\omega C\approx 1.257\mu \mathrm{S}$. A one-degree wave phase offset yields $\hat{C}\approx 22.775\mathrm{pF}$, an error of about $13.9\%$, despite perfect amplitude readings. These are chosen port-model values, not measured device specifications.

A useful measurement repeats the estimate over frequency and excitation amplitude. A nearly constant fitted $C$ and a residual consistent with $G+i\omega C$ support the assumed model; they do not prove that all parasitic effects were removed. A known fixture admittance adds to a parallel port and must be subtracted or retained in the model. At very small susceptance, uncertainty in the relative wave phase can dominate, so a high DC input impedance alone is not evidence for a precise capacitance measurement.

Input impedance is the ratio of a small applied input-voltage phasor to the resulting input-current phasor, with the output termination and operating point specified. A finite input impedance loads a voltage source. For an ideal operational amplifier the input impedance is infinite, so neither input terminal draws current.

An instrumentation amplifier amplifies a differential input while presenting high input impedance and rejecting a common component. A useful ideal relation isIts common-mode rejection ratio describes finite unwanted response to common-mode voltage. This is distinct from the amplifier input common-mode range over which the circuit can operate without internal saturation.^[ref]

For an original example, stipulate $v_{+}=2.501\mathrm{V}$, $v_{-}=2.499\mathrm{V}$, $G=100$ and $V_{\mathrm{ref}}=2.5\mathrm{V}$. The differential signal is $2\mathrm{mV}$ and the ideal output is $2.7\mathrm{V}$, assuming all input and output limits are satisfied.

Now suppose the differential-to-common gain ratio is $10^4$, or $80\mathrm{dB}$. The common-mode gain is then $100/10^4=0.01$. A $1\mathrm{V}$ common-input change contributes $10\mathrm{mV}$ at the output, five percent of the desired $0.20\mathrm{V}$ signal contribution. A high rejection ratio therefore does not mean zero error.

A source that changes both inputs together tests rejection; a source that changes their difference tests differential gain. Both tests must respect input common-mode limits, amplifier output range, load and frequency response. A plausible ideal output value alone does not prove that every internal stage remains linear.

Connect a resistor $R_{\mathrm{in}}$ from the input source to the inverting input, a feedback resistor $R_f$ from output to that same input, and ground the non-inverting input. For ideal linear operation the inverting node is a virtual ground. Kirchhoff's current law gives $V_i/R_{\mathrm{in}}+V_o/R_f=0$, yielding the displayed voltage gain. The source sees input impedance $R_{\mathrm{in}}$, even though the amplifier input itself has infinite input impedance.

Joseph Wu is the named author of Texas Instruments' 2018 guide to resistance thermometer measurements, revised in 2023. The guide connects sensor wiring, excitation electric current, reference resistors and analog-to-digital converters rather than treating the converter as a complete thermometer by itself.^[ref]

One concrete design distinction is between two-wire resistance measurement and four-terminal sensing. In the two-wire arrangement, the same leads carry excitation electric current and contribute to the measured electric potential difference. Their electrical resistance is therefore counted with the sensor. Separate sense leads with high input impedance can exclude that series drop, although input leakage and other nonidealities still require attention.^[ref]

For an original ideal example, let a sensor have electrical resistance $R_T=100\Omega$, with two $1\Omega$ leads carrying $I=1\mathrm{mA}$. Two-wire resistance measurement givesThe $2\Omega$ lead error remains even when a shared reference resistor cancels excitation variations in the ratiometric measurement. Ideal four-terminal sensing instead measures $I{R}_T=100\mathrm{mV}$ directly across the sensor. This illustrates the platinum resistance thermometer lead resistance error mechanism without assuming a particular resistance-to-temperature calibration.

A proposed bench comparison replaces the sensor with a stable calibrated resistor and adds known series resistors to its current leads. Comparing two-wire and four-terminal sensing readings then tests lead-drop rejection without changing sensor temperature. The calculation distinguishes the wiring error from sensor self-heating in a ratiometric resistance measurement, which changes the sensor's actual electrical resistance.

Keithley Instruments is an instrument manufacturer associated with precision electrical measurement. Its Low Level Measurements Handbook, Seventh Edition by Keithley Instruments explains how current sources, voltmeters and connection arrangements determine what a low-level reading means, with concrete treatments of lead resistance and thermoelectric offset.^[ref]

A useful example is the handbook's comparison of two-wire resistance measurement with four-terminal sensing. In two-wire measurement, current and voltage readout share the leads, so their resistance contributes to the measured drop. Separate voltage-sensing connections can avoid including that lead drop when sensing current is negligible.^[ref]

For an original ideal calculation, a $1\Omega$ resistor has two current leads of $0.1\Omega$ each. At $10\mathrm{mA}$, the total drop is $12\mathrm{mV}$, giving $1.2\Omega$ if all of it is attributed to the specimen. A separate voltmeter connected directly across the specimen, with negligible sensing current, instead measures $10\mathrm{mV}$ and gives $1\Omega$.

That result follows from the connection arrangement, rather than from the manufacturer's name. Finite input impedance, contact placement, thermoelectric offset and source uncertainty can still matter. The manufacturer's technical handbook is useful as an apparatus-level account of such limits; its example methods do not establish the accuracy of an unspecified instrument or a particular laboratory setup.

Manufacturer's data sheet, revision D, October 2015.

Section 6.5, p. 5, gives typical input impedance $2\mathrm{M\Omega }$ at $25^{\circ }\mathrm{C}$ and typical large-signal voltage gain $200V/mV$. Section 7.4.2 describes closed-loop feedback. These are device-specific examples for interpreting a real operational amplifier.

Loaded voltage gain is the ratio of an amplifier's output to input signal electric potential differences with a specified load connected. In a small-signal model, let the open-circuit output be $v_{\mathrm{oc}}=A_0{v}_{\mathrm{in}}$ and let the complete amplifier have output impedance $Z_o$. A load $Z_L$ then givesThis is the voltage divider result from Thévenin's theorem at the output terminals. The university source explains why a linear circuit can be replaced at specified terminals by a source and series impedance.^[ref] The output impedance used here must describe the complete amplifier at the stated operating point and frequency, including its feedback.

The input terminal matters too. For a generator $v_s$ with source impedance $Z_s$ driving amplifier input impedance $Z_i$, the corresponding source-to-load ratio in a unilateral model isThis includes both input and output loading; it differs from the terminal-to-terminal voltage gain defined above.

For an original resistive example, choose $A_0=12$, $Z_o=100\Omega$, $Z_L=900\Omega$, $Z_i=1\mathrm{k\Omega }$ and $Z_s=50\Omega$. The loaded terminal gain is $10.8$, while the source-to-load gain is $72/7\approx 10.286$. Reducing the load to $100\Omega$ makes the terminal gain six, even though the stipulated open-circuit gain remains twelve. These are model parameters, not device specifications.

A direct test holds the actual amplifier input signal fixed, changes a known load and measures the output with an oscilloscope whose probe impedance is included in the effective load. Use small enough signals to retain linear operation and respect the amplifier output range. If the output-to-input ratio changes with loading, an unloaded gain alone is insufficient to predict the circuit's behavior.

At nonzero frequency the impedances and gain can be complex. A reactive-load phase shift in a finite-output-impedance amplifier can change both magnitude and phase, while input-output coupling or nonlinear current limiting can invalidate this simple unilateral divider model. The ideal feedback resistance-ratio examples in the manufacturer's introduction apply within their corresponding operating assumptions.^[ref]

The load impedance $Z_L$ is the terminal electrical impedance of the receiving electrical load, at a stated frequency and operating condition. With electric current defined as entering the load's positive-voltage terminal, sinusoidal steady-state phasors obeyThe complex number records both the amplitude ratio and the phase difference. It belongs to the selected terminals and model; an arbitrary nonlinear device need not have a single amplitude-independent impedance.

A resistor gives $Z_L=R$. A series resistor and capacitor giveFor $R=1\mathrm{k\Omega }$, $C=1\mu \mathrm{F}$ and $f=1\mathrm{kHz}$, this is about $(1000-159.15\mathrm{i})\Omega$, with magnitude $1012.59\Omega$ and phase $-9.04^{\circ }$. Load electric current leads its terminal electric potential difference in this example. The component laws and phasor interpretation follow the sinusoidal circuit model.^[ref]

The load changes the source's operating point. A source with open-circuit phasor $V_s$ and series impedance $Z_s$ suppliesFor RMS phasors, the complex power entering the load is $S_L=V_L{I}_L^{\ast }$. Its real part is the mean delivered power,Using peak rather than RMS amplitudes would introduce a factor $1/2$ in that power expression.

An original resistive example has $V_s=1\mathrm{V}$ RMS and $R_s=1\mathrm{k\Omega }$. A $9\mathrm{k\Omega }$ load draws $0.100\mathrm{mA}$, receives $0.900\mathrm{V}$ and dissipates $0.090\mathrm{mW}$. A $1\mathrm{k\Omega }$ load instead receives $0.500\mathrm{V}$ and dissipates $0.250\mathrm{mW}$. More delivered power need not mean a smaller voltage error.

The input impedance of an instrument is a load when the instrument is connected to a source. High-input-impedance buffering reduces this interaction in voltage measurements.^[ref] Impedance bridging prioritizes preserving the source signal; impedance matching addresses other objectives such as maximum power transfer under its assumptions.