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An actual teaching experiment turns the phasor definition into readings. Leipzig University's laboratory handout Measurements with an oscilloscope, experiment E 3e, uses a function generator, a two-channel oscilloscope, a known resistor and a capacitor. Figure 5 places the capacitor above the resistor, with a common return below the resistor. Channel 1 measures the applied terminal electric potential difference $v_1$; channel 2 measures $v_R$. The handout asks for peak-to-peak values and relative timing, then comparison of measured and calculated electrical impedances with $R=3\mathrm{k\Omega }$, $C=0.47\mu \mathrm{F}$ at $100$ and $300\mathrm{Hz}$. It also asks students to check the oscilloscope time base against a digitally counted generator frequency. These are apparatus and procedural specifications, not reported measured results.^[ref]

For this arrangement, Ohm's law gives $i(t)=v_R(t)/R$ if probe loading and the sensing resistor's electrical reactance are negligible. Record both voltage magnitudes with the same convention: peak, peak-to-peak, or root mean square. After the transient settles, compare matched rising zero crossings $t_1$ of $v_1$ and $t_R$ of $v_R$, with period $T=1/f$. ThenThe recovered electrical impedance includes the known resistor. For a separate unknown component in series with that resistor, subtract $R$ from the inferred total electrical impedance. A current crossing earlier than the applied voltage crossing gives $\Delta t<0$, hence negative $\varphi$. For the stipulated series RC impedance example at $1000\mathrm{Hz}$, this predicts $\Delta t=-0.160717\mathrm{ms}$; it is a calculated timing, not a lab observation. Timing supplies the complex argument that an amplitude ratio alone cannot recover.

As additional measurement controls, first feed the same sinusoid to both channels to check relative delay and polarity; then replace the reactive chain with a known resistor, expecting nearly zero phase difference. Keep both probe returns at the common return shown in figure 5. A reversed voltage polarity adds half a turn to its inferred wave phase. Match crossings with the same slope and choose $-T/2<\Delta t\le T/2$; adjacent cycles otherwise change $\varphi$ by a full turn. A sweep continuous in frequency helps track that branch. These controls test the signed inference rather than assuming that the scope's delay readout has the desired sign.

Measure the loaded terminal electric potential difference on channel 1 at every frequency. The generator's output impedance can change the applied magnitude; its front-panel setting is not the measured terminal value. The generator's internal electrical impedance is outside the terminal ratio above, while the known sensing resistor is inside it. Probe loading, finite timing resolution, component tolerances and distorted waveforms limit the inference. A repeat at lower drive amplitude tests whether one linear electrical impedance still fits. Electrical reactance bench measurement develops these loading and reference-direction issues further.

Consider an op amp integrator with infinite input impedance, an internal controlled voltage $u=-A(s)v$ where $v$ is the inverting-input voltage, and a series output impedance equal to a resistance $r_o$. Assume no external output load. Writing $y$ for the output, Kirchhoff's current law givesEliminating $u$ and $v$ yieldsThe expression at $r_o=0$ is obtained by its limit. In particular, constant gain $A_0$ and $r_o=0$ give $H(s)=-A_0/[1+sRC(1+A_0)]$: a finite direct-current gain followed by an integrating regime. For the dominant-pole model $A(s)=A_0/(1+s/{\omega }_a)$ and $r_o=0$,If $A_0\gg 1$ and $A_0{\omega }_{a}RC\gg 1$, there are separated turnover frequencies near $1/(A_{0}RC)$ and $A_0{\omega }_a$. The gain magnitude is respectively constant, proportional to ${\omega }^{-1}$ and proportional to ${\omega }^{-2}$. With the convention $e^{i\omega t}$ a continuous phase choice passes from $180^{\circ }$ through $90^{\circ }$ to $0^{\circ }$. If $r_o>0$ and $A(i\omega )\to 0$, capacitive feedthrough instead gives the ultimate limit $r_o/(R+r_o)$. Specifying finite gain alone therefore does not specify a unique high-frequency response.

With the noninverting input grounded, a differential input impedance $R_{\mathrm{in}}$ draws current from the summing node. For zero output impedance, $V_o=-Av$ and Kirchhoff's current law gives $(v-V_i)/R_1+(v-V_o)/R_2+v/R_{\mathrm{in}}=0$. Eliminating $v$ yields the displayed voltage gain. The resistor-ratio result requires $|A|\gg 1+R_2/R_1+R_2/R_{\mathrm{in}}$ as well as stable, unsaturated operation. The same expression applies to small-signal phasors with complex $A(f)$.

An ideal operational amplifier has infinite open-loop gain and input impedance, zero output impedance, unlimited response speed and zero input offset voltage and input bias current. Its input currents vanish. In a stable linear circuit with negative feedback and a finite output, its differential input voltage tends to zero as the open-loop gain tends to infinity. Thus $i_{+}=i_{-}=0$ and $v_{+}=v_{-}$ are the familiar conditional circuit rules. The equality of the input voltages cannot be imposed on an open-loop, unstable or saturated circuit.

Impedance bridging, also called voltage bridging, connects a source to a much higher load impedance so that little signal electric potential difference is lost across the source's output impedance. It is useful when the receiver should observe a signal while drawing little electric current from its source.

Represent a linear source at one frequency by open-circuit phasor $V_s$ and series electrical impedance $Z_s$. With receiving input impedance $Z_L$, the voltage divider givesThus $|Z_s/Z_L|\ll 1$ makes $H$ close to one as a complex number, controlling both amplitude and phase loading. For positive electrical resistances, the relative voltage loss is $R_s/(R_s+R_L)$. A $1\mathrm{k\Omega }$ source feeding $99\mathrm{k\Omega }$ retains $99\%$ of its open-circuit voltage; feeding $9\mathrm{k\Omega }$ retains $90\%$.

For a tolerance $\eta$ on that resistive relative loss,The often convenient ten-to-one ratio is therefore a chosen accuracy compromise, not a universal definition. A one-percent limit requires at least a ninety-nine-to-one ratio in this ideal resistive model. Voltage divider loading error gives the related loading problem when the source is itself a divider.

Impedance bridging with capacitive input explains why a large DC electrical resistance is not enough at every frequency. With source resistance $R_s$ and receiving $R_{\mathrm{in}}$ in parallel with capacitance $C_{\mathrm{in}}$,At $R_s=1\mathrm{k\Omega }$ and $R_{\mathrm{in}}=1\mathrm{M\Omega }$, the DC ratio is about $0.999$. With $C_{\mathrm{in}}=100\mathrm{pF}$, its magnitude at $1\mathrm{MHz}$ is only about $0.846$. The capacitive path loads the source despite the high DC input resistance.

Texas Instruments' three-amplifier presentation motivates high-input-impedance buffering by explicitly showing that source current and nonzero source output impedance degrade accuracy.^[ref] A buffer changes the load seen by the signal source; its own finite input and output behavior still matter.

Impedance matching has a different objective in maximum-power-transfer applications. For a resistive source, choosing equal source and load resistances gives half the open-circuit voltage, whereas bridging seeks a ratio near one. Signal fidelity, delivered power and high-frequency transmission behavior require their appropriate models.

Impedance bridging with capacitive input treats a receiver's input as a resistance in parallel with a capacitance. Even when its DC input impedance is large, the capacitive path can draw appreciable electric current at higher frequency, changing both the amplitude and phase of the observed electric potential difference.

For source resistance $R_s$, receiving resistance $R_{\mathrm{in}}$ and input capacitance $C_{\mathrm{in}}$, use sinusoidal steady-state phasors and a linear source model. The receiving electrical admittance is $1/R_{\mathrm{in}}+\mathrm{i}\omega C_{\mathrm{in}}$, soHere $V_s$ is the open-circuit source phasor; $V_L$ is the loaded terminal phasor. The impedance bridging objective is $H$ near one, rather than merely a large quoted DC input resistance.

The amplitude and phase responses areAn amplitude-only tolerance and a tolerance on the full complex number express different requirements. The latter measuresFor positive resistances, capacitance and a chosen $0<\eta <1$, the capacitive bridging complex-error bandwidth condition $|1-H|\le \eta$ requiresA negative numerator means even the DC loading error exceeds the tolerance.

In an original example, $R_s=1\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$ and $C_{\mathrm{in}}=100\mathrm{pF}$ give $g=0.001$. A one-percent complex-error tolerance permits frequencies only up to about $15.9\mathrm{kHz}$. At $100\mathrm{kHz}$ the amplitude ratio remains about $0.997$, but the phase is about $-3.59^{\circ }$ and the complex error about $0.0627$. A small amplitude error can coexist with a materially larger waveform-phase error.

High-input-impedance buffers are motivated by just this source-loading problem. Texas Instruments' three-amplifier presentation shows how current drawn from a source with finite output impedance degrades accuracy and how input buffers reduce loading.^[ref] The chosen component values above are not specifications of a particular amplifier. A real receiver may require additional input paths, frequency-dependent source impedance and a model of the connected cable or probe.

A voltage gain determines a power gain only when the electrical conditions at both ports are included. The familiar equality between $20{\log }_{10}|A_v|$ and $10{\log }_{10}{G}_P$ requires a particular impedance relation; it is not a conversion between arbitrary voltage and power ratios.

Use phasors whose moduli are root mean square amplitudes, at one sinusoidal frequency. At a load with electrical impedance $Z$ and electrical admittance $Y=1/Z$, the current is $I=YV$. Its complex electrical power is $V{I}^{\ast }$, with the complex conjugate arising from the relative phase of the two sinusoids. Averaging $v(t)i(t)$ over a cycle gives the active powerTo see the averaging step, write $v(t)=\sqrt{2}|V|\cos (\omega t+{\varphi }_V)$ and similarly for $i(t)$. The product's cycle average is $|V||I|\cos ({\varphi }_V-{\varphi }_I)$, the real part of $V{I}^{\ast }$. Peak-amplitude phasors instead require an extra factor $1/2$.

Let $Y_{\mathrm{in}}$ describe the actual input impedance and $Y_L$ the actual load impedance. Take $\mathrm{Re}{Y}_{\mathrm{in}}>0$ and $\mathrm{Re}{Y}_L>0$ with nonzero terminal signals, and define currents into the amplifier at the input and into the load at the output. With the measured loaded voltage gain $A_v=V_L/V_{\mathrm{in}}$,Thus $G_P=|A_v{|}^2$ requires equality of the relevant electrical conductances, not merely equality of impedance moduli. For example, input $Z_{\mathrm{in}}=50\Omega$ and load $Z_L=(30+40i)\Omega$ both have modulus $50\Omega$, but their electrical admittances have real parts $0.020$ and $0.012\mathrm{S}$. The multiplier is $0.6$, so $G_P=0.6|A_v{|}^2$.

For real resistive ports this becomesTake an original example with measured $|A_v|=0.5$, $R_{\mathrm{in}}=10\mathrm{k\Omega }$ and $R_L=50\Omega$. The voltage gain is $-6.02\mathrm{dB}$, while the power gain is $50$, or $16.99\mathrm{dB}$. An active buffer can reduce the signal's electric potential difference while delivering more signal power than it accepts at its input; the supply provides the additional energy.

The amplifier's output impedance is distinct from the connected load impedance. To show why that distinction matters, model its output by a Thévenin equivalent with open-circuit voltage $A_0{V}_{\mathrm{in}}$ and series resistance $R_o$. The voltage divider givesWith $A_0=0.6$ and $R_o=10\Omega$, the $50\Omega$ load produces the preceding $A_v=0.5$ example. Differentiating $R_L/(R_o+R_L{)}^2$ gives $(R_o-R_L)/(R_o+R_L{)}^3$, so delivered power is largest at $R_L=R_o$, as in the maximum power transfer theorem. Here its power gain is $90$. Increasing $R_L$ much further makes $A_v$ approach $A_0$ but reduces delivered power. That high-load-impedance regime is impedance bridging, useful for sensing the source's voltage with little loading.

A bench demonstration uses a function generator, a known termination and an oscilloscope. The Keysight guide explains that an expected-load setting changes how amplitude is displayed for generators with a fixed series output impedance; a high-impedance load can receive twice the voltage expected for a matched $50\Omega$ termination.^[ref] As an independent low-frequency resistive calculation, an open-circuit source of $1\mathrm{V}$ root mean square with $50\Omega$ series resistance delivers $0.5\mathrm{V}$ and $5\mathrm{mW}$ to $50\Omega$. Into $1\mathrm{M\Omega }$ it delivers about $0.99995\mathrm{V}$ but only $1.00\mu \mathrm{W}$. The larger terminal reading accompanies much less delivered power. Specify the actual load, frequency and amplitude convention when comparing gain measurements.

Loaded voltage gain is the ratio of an amplifier's output to input signal electric potential differences with a specified load connected. In a small-signal model, let the open-circuit output be $v_{\mathrm{oc}}=A_0{v}_{\mathrm{in}}$ and let the complete amplifier have output impedance $Z_o$. A load $Z_L$ then givesThis is the voltage divider result from Thévenin's theorem at the output terminals. The university source explains why a linear circuit can be replaced at specified terminals by a source and series impedance.^[ref] The output impedance used here must describe the complete amplifier at the stated operating point and frequency, including its feedback.

The input terminal matters too. For a generator $v_s$ with source impedance $Z_s$ driving amplifier input impedance $Z_i$, the corresponding source-to-load ratio in a unilateral model isThis includes both input and output loading; it differs from the terminal-to-terminal voltage gain defined above.

For an original resistive example, choose $A_0=12$, $Z_o=100\Omega$, $Z_L=900\Omega$, $Z_i=1\mathrm{k\Omega }$ and $Z_s=50\Omega$. The loaded terminal gain is $10.8$, while the source-to-load gain is $72/7\approx 10.286$. Reducing the load to $100\Omega$ makes the terminal gain six, even though the stipulated open-circuit gain remains twelve. These are model parameters, not device specifications.

A direct test holds the actual amplifier input signal fixed, changes a known load and measures the output with an oscilloscope whose probe impedance is included in the effective load. Use small enough signals to retain linear operation and respect the amplifier output range. If the output-to-input ratio changes with loading, an unloaded gain alone is insufficient to predict the circuit's behavior.

At nonzero frequency the impedances and gain can be complex. A reactive-load phase shift in a finite-output-impedance amplifier can change both magnitude and phase, while input-output coupling or nonlinear current limiting can invalidate this simple unilateral divider model. The ideal feedback resistance-ratio examples in the manufacturer's introduction apply within their corresponding operating assumptions.^[ref]

An operational amplifier is a differential electronic amplifier whose unloaded voltage is modeled in its linear regime by $v_o=A(s)(v_{+}-v_{-})$. Its large open-loop gain, large input impedance and small output impedance make negative feedback useful for setting a reproducible transfer function with external components. Supply voltages bound the available output swing; the linear model does not apply after saturation.

The passive RC low-pass filter is simple, inexpensive, requires no power supply, and has no operational amplifier saturation or finite bandwidth limitation. It offers no voltage gain; its output impedance is finite, and both source electrical resistance and loading can change the observed frequency response. Its resistor also produces thermal noise.

The active inverting low-pass amplifier provides a low-frequency voltage gain of magnitude five and, within the usable bandwidth, a small output impedance, so it can drive a load with much less change in frequency response. The input electrical resistance is approximately $R_1=1\mathrm{k}\Omega$ and may itself load the source. It needs a power supply and adds electrical noise and offset; finite operational amplifier gain, bandwidth, slew rate, available output swing, and output electric current limit the ideal formula. Its inversion must also suit the application. The best choice depends on required voltage gain, source and load electrical impedances, and the signal's frequency and amplitude.

An ideal operational amplifier has infinite input impedance, so neither input draws electric current, and zero output impedance, so its prescribed output voltage is independent of the output electric current within the ideal model. These are the two additional assumptions needed here.

An ideal operational amplifier has infinite input impedance and open-loop gain, zero output impedance and no offsets or response limits. Its input currents vanish. Stable operational-amplifier negative feedback, a finite output and unsaturated linear operation then imply a virtual short, $v_{+}=v_{-}$. Real amplifiers have finite frequency-dependent gain, input bias currents, offset voltage, output loading, finite bandwidth, slew rate and supply-rail limits. Equal input voltages cannot be assumed in an open-loop or saturated circuit.

Here the noninverting input is grounded. In the ideal-feedback limit the inverting node is a virtual ground, so the resistor current charges the feedback capacitor:The initial capacitor charge fixes the integration constant. This is an op amp integrator, with $H(i\omega )=-1/(i\omega RC)$.

A tiny direct-current input, input bias current or offset can drive the output towards saturation. A parallel feedback resistor $R_f$ provides a direct-current return path, giving $H(s)=-(R_f/R)/(1+s{R}_{f}C)$; choose $\omega R_{f}C\gg 1$ over the intended integration band. A reset switch sets initial charge; low-offset components and suitable signal amplitude reduce drift and saturation. The useful band must also remain below the amplifier's bandwidth and slew-rate limits.

For the stipulated finite but constant real gain $A=100$, infinite input impedance and negligible output impedance, write the inverting-node voltage as $v=-V_{\mathrm{out}}/A$. With phasors proportional to $e^{i\omega t}$,ThereforeThe low-frequency gain is $-100$. The corner is ${\omega }_c=1/(101RC)$; above it the amplitude falls as $100/(101\omega RC)$ and the phase approaches $+\pi /2$. phase $+\pi$ and $-\pi$ describe the same low-frequency inversion. This finite-gain circuit is a low-pass response with an integrating high-frequency regime, not an ideal integrator down to zero frequency. A genuinely frequency-dependent $A(i\omega )$ would introduce additional high-frequency limitations beyond this specified model.

An ideal operational amplifier draws no current at either input. With stable operational-amplifier negative feedback in its unsaturated linear range, infinite open-loop gain also gives a virtual short, $V_{+}=V_{-}$. The amplifier adjusts its output to enforce that equality; it is not a conducting connection between the inputs. Here $V_{+}=0$, so the ideal summing node is a virtual ground. Kirchhoff's current law gives $V_{\mathrm{in}}/R_1=-V_{\mathrm{out}}/R_2$, hence the ideal gain is $-R_2/R_1$.

For the finite-input-resistance inverting amplifier let the inverting-node voltage be $v$, and continue to neglect output impedance. The controlled output and node-current balance areEliminating $v$ givesDividing the denominator by $R_2$ gives the requested resistance-sum form. The ideal result follows whenever $|A|\gg 1+R_2/R_1+R_2/R_{\mathrm{in}}$; taking $R_{\mathrm{in}}\to \infty$ alone is insufficient if $A$ is small. At finite frequency $A$ and the gain are phasor ratios, subject to feedback stability.

With equal resistors and sufficiently large loop gain, $V_{\mathrm{out}}\simeq -V_{\mathrm{in}}$. This gives a controlled sign reversal or 180-degree phase inversion, useful for subtraction and opposite-phase signal paths, with amplitude set by a resistor ratio rather than uncertain open-loop gain. The source still sees approximately $R_1$, so this is not a high-input-impedance voltage follower. For the ideal-input, single-pole model, the noise gain of an operational amplifier is two and the closed-loop bandwidth is approximately half the gain-bandwidth product. Output swing, slew rate and load constraints must also permit linear operation.

An ideal operational amplifier has infinite differential open-loop gain, infinite input impedance, zero output impedance and unlimited bandwidth and output capability, and zero input offset voltage and input bias current. In a stable negative-feedback circuit operating linearly, its input currents vanish and $V_{-}=V_{+}$. This equality is a feedback consequence, not a rule for a saturated or open-loop amplifier. Here the grounded non-inverting input makes the inverting node a virtual earth.

The inverting two-pole band-pass filter has a series resistor and capacitor input, while the feedback arm is a parallel resistor and capacitor. With Laplace variable $s$,Kirchhoff's current law at virtual earth gives the minus sign. Substituting $s=i\omega$ yieldsIt vanishes at zero and infinite frequency, with low-frequency $|H{|}^2\simeq (\omega R_2{C}_1{)}^2$ and high-frequency $|H{|}^2\simeq 1/(\omega R_1{C}_2{)}^2$. Differentiation gives the single maximumFor ${\tau }_1\gg {\tau }_2$, the broad interval $1/{\tau }_1\ll \omega \ll 1/{\tau }_2$ has $|H|\simeq R_2/R_1$. For ${\tau }_2\gg {\tau }_1$, the interval $1/{\tau }_2\ll \omega \ll 1/{\tau }_1$ instead has $|H|\simeq C_1/C_2$. The same rising and falling asymptotes apply outside either plateau.

Writing $a={\tau }_1+{\tau }_2$ and $b={\tau }_1{\tau }_2$, the half-power frequencies and quality factor areEqual time constants give the narrowest fractional pass-band achievable here, with ${\omega }_{\pm }=(\sqrt{2}\pm 1){\omega }_0$ andThis topology cannot make a genuinely sharp, high-$Q$ band-pass. Its poles are real, and the selectivity bound for a two-real-pole band-pass prevents arbitrarily narrow selection. A more selective resonant filter needs additional circuit structure. The gain above answers the component-ratio question for the sharpest available setting without assuming an impossible limit.

Real amplifiers have finite frequency-dependent gain and phase lag, so virtual earth becomes inaccurate, the response changes and stability must be checked. Gain-bandwidth limits, slew rate for large signals, output loading and amplifier saturation also matter. Component tolerances move the corners; capacitor parasitics, stray capacitance, resistor noise and input noise become significant. The ideal high-frequency tail should not be extrapolated beyond the amplifier and lumped-component operating ranges.

In an operational-amplifier negative feedback loop, an operational amplifier has large open-loop gain $A$, with $V_o=A(V_{+}-V_{-})$. Feeding a fraction $\beta V_o$ back to the inverting input opposes an output increase. For a non-inverting signal input,Its sensitivity to open-loop gain changes is reduced by $d\ln A_{\mathrm{cl}}/d\ln A=1/(1+A\beta )$. Thus resistor ratios can set a reproducible gain despite device variation; feedback also suppresses internal distortion and reduces output impedance. Gain is traded for usable bandwidth, subject to the amplifier's frequency response.

For the non-inverting connection, place $R_f$ between output and inverting input and $R_g$ between that input and ground. Then $\beta =R_g/(R_f+R_g)$, giving gain $1+R_f/R_g$. For an inverting connection, ground the non-inverting input, inject the signal through $R_{\mathrm{in}}$ and return $R_f$ from output to the inverting node. Small differential input and negligible input current then give gain $-R_f/R_{\mathrm{in}}$. The near-zero node is a virtual ground, not a physical ground connection.

The feedback must remain stable at the frequencies where loop gain matters. Extra phase lag can turn the intended opposition into oscillation; adequate phase margin, supply headroom, input common-mode range, output-current capability and slew rate are required. Feedback neither prevents clipping nor removes all input noise.^[ref]

An ideal operational amplifier has infinite differential open-loop gain, infinite input impedance, zero output impedance, unlimited bandwidth and slew rate, and zero input offset voltage, input bias current and intrinsic noise. The idealized model has no finite output-swing or output-current limit.

The usual circuit rules areThe first follows from infinite input impedance. The second follows because a finite output requires $v_{+}-v_{-}=v_o/A\to 0$ as the open-loop gain tends to infinity. It is a virtual equality of potentials, not a conducting connection between the inputs. It cannot be imposed for open-loop operation or after an amplifier reaches its supply rails.

A real operational amplifier has large but finite, frequency-dependent open-loop gain; the gain falls and its phase changes at higher frequencies. Finite bandwidth and slew rate constrain small-signal and large-signal responses respectively. There are also finite input impedance and output impedance, nonzero input bias currents and input offset voltage, and internally generated noise. Offset and bias can drift with temperature.

The output is limited by the supply voltages and output-current capability, and the inputs have a permitted common-mode range. Rejection of common-mode and supply changes is finite. Consequently $v_{+}-v_{-}$ need not vanish exactly, and neither the virtual-ground approximation nor linear gain formulas apply after saturation. For the calculation below the stipulated infinite input impedance removes the input loading currents, while finite gain and optionally finite output resistance are retained.

A non-ideal amplifier is not specified by infinite input impedance alone: its open-loop gain and output impedance must also be modeled. Take its internal controlled output to be $u=-A(s)v$, where $v$ is the inverting-input potential, and place a resistance $r_o$ between $u$ and the actual output $y=V_{\mathrm{out}}$. The non-inverting input remains grounded; assume no external load. This gives an explicit finite-gain operational-amplifier integrator model.

Writing Kirchhoff's current law at the input and output nodes givesThe second equation gives $y=(sC{r}_o-A)v/(1+sC{r}_o)$. Substitution in the first gives the general transfer functionFor sinusoidal phasors, set $s=i\omega$. The numerator and denominator are complex, so the magnitude gives the amplitude ratio and their arguments give the relative phase.

The simplest model takes $r_o=0$ and a constant finite gain $A_0>0$. It givesThus below ${\omega }_l=[(1+A_0)RC{]}^{-1}$ the amplifier has gain magnitude $A_0$ and inversion. Above that frequency it approaches an integrator with magnitude $A_0/[(1+A_0)\omega RC]\simeq 1/(\omega RC)$ and phase $+90^{\circ }$. Constant finite gain by itself predicts no further high-frequency turnover.

For a more realistic sketch, use the standard dominant-pole open-loop gain $A(s)=A_0/(1+s/{\omega }_a)$, still with $r_o=0$. ThenThe exact frequency response isAssuming $A_0\gg 1$ and $A_0{\omega }_{a}RC\gg 1$, the turnover frequencies are well separated: ${\omega }_l\simeq 1/(A_{0}RC)$ and ${\omega }_h\simeq A_0{\omega }_a$, the approximate unity-gain angular frequency of the amplifier. The regimes arewith magnitude slopes $0,-20,-40\mathrm{dB}$ per decade and smooth phase transitions. This is the solid curve in the figure; $180^{\circ }$ and $-180^{\circ }$ denote the same phase.

If finite $r_o$ is retained and $A(i\omega )\to 0$, the general expression instead approaches $r_o/(R+r_o)$ at very high frequency: the capacitor couples the input to the output through a passive voltage divider. The dashed curve illustrates that eventual feedthrough. Other amplifier poles or an external load would alter the response again. No particular values of $A_0,{\omega }_a,r_o$ are given in the paper, so the numerical sketch is illustrative and the general expression states the model dependence explicitly.

The University of Colorado Boulder's Lab 3: Filters, §§7.1–7.4, specifies measuring the resistor and capacitor, then driving the assembled RC low-pass filter with a function generator. A two-channel oscilloscope reads actual input and output using high electrical impedance. Sweep the frequency, record the voltage amplitude ratio, and locate $1/\sqrt{2}$. A control compares a cable with a $10\times$ oscilloscope probe on a resistive voltage divider, isolating measurement capacitance before using the probe for the filter. A slow square wave then lets discharge timing estimate the time constant independently. Agreement supports the RC low-pass frequency response; source output impedance, probe loading, and instrument signal bandwidth limit it. These are prescribed measurements, with no measured dataset supplied here.^[ref]

The two-channel setup can also test the predicted phase difference directly: for positive frequency $f$, measure the output's time lag $\Delta t$ between corresponding features of the two sinusoids. For this single-stage model the phase lies between $-\pi /2$ and $0$, so choose the lag within a quarter cycle and calculate $\varphi =-2\pi f\Delta t$. At the cutoff frequency the predicted lag is one eighth of a cycle. This tests the timing part of the frequency response as well as the voltage ratio.

A real electrical load can draw electric current from the output. For a load resistor $R_L>0$ across the capacitor, Kirchhoff's current law instead givesTherefore the loaded continuous-time frequency response isLoading reduces the eventual gain and shortens the time constant. With the constructed values and $R_L=10\mathrm{k}\Omega$, $K_L\approx 0.81967$, ${\tau }_L\approx 84.754\mu \mathrm{s}$, and the corner relative to the loaded low-frequency gain moves to $1.8778\mathrm{kHz}$. A $3\mathrm{V}$ step now approaches $2.4590\mathrm{V}$. A quicker rise alone would conceal the error in the final voltage.

With the ideal input voltage source set to zero, the output impedance seen by the electrical load isThis follows from Thévenin's theorem: the resistor and capacitor are then in parallel. A sufficient small-loading condition is $|Z_L(\omega )|\gg |Z_{\mathrm{out}}(\omega )|$ over the frequencies of interest. An oscilloscope is itself an electrical load: its input electrical resistance and cable or probe capacitance can both change the response. Pure extra parallel capacitance increases $C$ and lowers the corner, whereas a finite parallel electrical resistance gives the different gain-and-corner changes above.

The definition of input also matters. If voltage is prescribed inside a source with series electrical resistance $R_s$, the unloaded response to that internal source uses $R+R_s$. If the actual voltage at the filter input terminal is measured, the ratio of output to that measured input still uses $R$. Measuring both terminals avoids mistaking a source setting for the voltage delivered to the filter.