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Side losses need not destroy the method. Let $\theta$ be the small temperature disturbance about a steady background in surroundings at fixed temperature. For a rod of cross-sectional area $S$ and perimeter $\mathcal{P}$, a uniform real surface heat transfer coefficient $h_s$ produces a loss per unit volume of $H\theta$, with $H=h_s\mathcal{P}/S$. Assume constant $k,\rho ,c_p,H$, a cross-section nearly uniform in temperature, and no distributed heat source. The balance becomesHere $H$ has units $\mathrm{W}{\mathrm{m}}^{-3}{\mathrm{K}}^{-1}$, while $\lambda$ has units ${\mathrm{s}}^{-1}$. This is a distributed version of Newton's law of cooling; a constant linearized contribution from thermal radiation may be included over a small temperature range. It does not represent arbitrary time-dependent coupling to a surrounding material with its own thermal storage.

For the decaying exponential branch, the phasor equation givesso thatReal positive side loss increases $a$ and decreases $b$ at fixed angular frequency and thermal diffusivity. Their product eliminates $\lambda$, yielding the combined inferenceThis result requires that attenuation and lag belong to the same exponential complex wavenumber at the same frequency, and that the loss term is real. It does not generally survive a superposition caused by a nearby finite end, spatially varying coefficients, transverse temperature gradients, or unequal sensor delays. The inferred $\lambda =\alpha (a^2-b^2)$ supplies an additional model check; a negative value signals inconsistency with this passive-loss model rather than negative physical cooling.

The capacitive bridging complex-error bandwidth is the largest frequency over which a receiving port preserves the source phasor within a specified complex relative gain error. The criterion includes phase shift as well as amplitude. A large DC input impedance alone cannot establish this bandwidth when input capacitance matters. The manufacturer's input models explicitly include resistive and capacitive paths.^[ref]

For the scalar impedance bridging with capacitive input model, assume a positive real source electrical resistance $R_s$, receiver resistance $R_{\mathrm{in}}>0$, and input capacitance $C_{\mathrm{in}}>0$ in parallel. Let $V_s$ be the unloaded source phasor. A voltage divider givesFor tolerance $0<\eta <1$, the complex relative gain error isIts square is strictly increasing in $x^2$, since its derivative is $(1+2g)/[(1+g{)}^2+x^2{]}^2>0$. Thus satisfying $E(f)\le \eta$ defines a continuous frequency interval starting at DC, whenever it is feasible. Rearranging givesThe DC error floor is ${\eta }_0=g/(1+g)$. If $\eta <{\eta }_0$, no frequency meets the tolerance; if $\eta ={\eta }_0$, only DC does. The boxed positive bandwidth applies when $\eta >{\eta }_0$.

For an original near-limit example, choose $R_s=10\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$ and $C_{\mathrm{in}}=100\mathrm{pF}$. Then $g=0.01$ and the DC error is about 0.9901 percent. A 1 percent full-complex tolerance leaves onlyAn amplitude-only 1 percent criterion, $|H|\ge 0.99$, instead allows about $2273.47\mathrm{Hz}$. The half-power (approximately $-3\mathrm{dB}$) signal bandwidth, relative to DC, is $(1+g)/(2\pi R_s{C}_{\mathrm{in}})\approx 160.75\mathrm{kHz}$. These are three distinct specifications of this same ideal model.

The square-root collapse of capacitive bridging bandwidth near the DC error floor follows by factoring the numerator:For fixed $g>0$ and $\eta \downarrow {\eta }_0$,This asymptotic equivalence explains the sharp loss of usable bandwidth when the resistive divider has already consumed nearly all the error allowance. Increasing $R_{\mathrm{in}}$ or reducing $R_s$ changes that floor; reducing only $C_{\mathrm{in}}$ rescales a feasible bandwidth but cannot remove infeasibility at DC.

The criterion also controls a complete waveform. Suppose a source waveform $v_s$ is both a square-integrable function and a bandlimited function, with spectrum supported where $|H-1|\le \eta$. For the corresponding zero-state response $v_L$, the Fourier transform of $v_L-v_s$ is $(H-1){\hat{v}}_s$. The Plancherel theorem, or the norm bound for a Fourier multiplier on L2, givesHere the Fourier transform uses the frequency-in-hertz convention, so the displayed Plancherel theorem has no extra normalization factor. This bound includes waveform changes caused by phase. It applies to the zero-state response of the stated frequency response. Any additional homogeneous solution from initially stored energy contributes its own error.

A bench check therefore needs both amplitude ratio and phase shift, with probe and cable capacitance included in the port model. Magnitude-only observations determine $|H|$ without determining $|1-H|$. The formula describes this chosen passive input network; additional amplifier dynamics require their own transfer function.

Consider two voltage dividers across a common source, with impedances $Z_0,Z_1$ in one branch and $R_1,Z_p$ in the other. Equal midpoint voltage phasors imply $Z_0{Z}_p=R_1{Z}_1$. If $Z_0=R_0+1/(i\omega C_0)$, $Z_1=1/(i\omega C_1)$ and $Z_p=(1/R+i\omega C{)}^{-1}$, then separating real and imaginary parts proves $R_0=R_{1}C/C_1$ and $C_0=R{C}_1/R_1$. The topology, especially the parallel standard arm, is essential.

A centripetal amplitude-error budget allocates the permitted error in an oscillating centripetal correction between amplitude mismatch and phase mismatch. If the true correction amplitude is $A>0$, the applied amplitude is $\hat{A}>0$ and the relative phase is $\varphi$, phasor subtraction gives residual amplitudeThe first term remains even with perfect timing. The second consumes part of the same acceleration-error budget; their separate limits cannot both be set to the entire allowed residual.

Write $\hat{A}=A(1+ϵ)$. For small $ϵ$ and $\varphi$, the leading approximation isThis provides an approximate joint budget, rather than permission to allow the maximum phase error and maximum gain error simultaneously. For an original example, $A=4m/{\mathrm{s}}^2$ and residual limit $0.10m/{\mathrm{s}}^2$ give relative budget0.025. Assigning relative amplitude error0.015 leaves an approximate phase budget0.020rad. The exact formula, with $\hat{A}=4.06m/{\mathrm{s}}^2$, gives a slightly smaller bound of about0.01985rad.

A centripetal speed-gain error illustrates how the mismatch can arise. For $C=r{\omega }^2$, using radius $r+\delta r$ and a speed reading scaled by $g$ producesWith correct radius and $g=1.01$, the correction is2.01% high. In a small-ripple model whose constant speed and ripple amplitude are both scaled by the same sensor gain, the oscillating correction amplitude has this same gain factor. For $A=4m/{\mathrm{s}}^2$ that alone gives0.0804m/s² amplitude mismatch. The constant centripetal term also needs its own error check; budgeting only the ripple does not control it.

Rotating-frame components and the rotation reference are experimentally consequential: a primary MEMS-sensor study compares rotating transmission measurements with stationary housing accelerometers and reconstructs a timing reference.^[ref] The budgets above are original illustrative calculations. Actual limits require the relevant operating speeds, radii, frequency range and measurement calibration, alongside the centripetal phase-error tolerance.

A centripetal phase error is a mismatch in the phase of a time-varying centripetal correction relative to the signal being corrected. It is a frequency-specific form of centripetal timing error. A constant centripetal magnitude has no changing phase to misalign, but speed ripple gives an oscillating contribution. For angular velocity $\omega (t)={\omega }_0+\epsilon \cos \Omega t$, expansion of $r\omega (t{)}^2$ to first order in $\epsilon$ gives an oscillation of amplitude $A=2r{\omega }_0\epsilon$ when $r,{\omega }_0,\epsilon$ are positive.

Let the true oscillating correction be $A\cos \theta$ and the applied correction $A\cos (\theta -\varphi )$. Their difference isso its amplitude is $2A|\sin (\varphi /2)|$. Equivalently, phasor subtraction gives magnitude $|A(e^{-i\varphi }-1)|$. Even perfectly matched amplitudes do not guarantee cancellation when their phases differ.

For an original example, $r=0.020\mathrm{m}$, ${\omega }_0=100rad/s$ and $\epsilon =1rad/s$ give $A=4m/{\mathrm{s}}^2$. A phase lag0.10rad leaves amplitude $8\sin (0.05)\approx 0.3998m/{\mathrm{s}}^2$. The centripetal phase-error tolerance for residual amplitude at most $0.10m/{\mathrm{s}}^2$, choosing the small phase-error range around zero, isFor a pure delay $\varphi =\Omega \tau$ at $\Omega =20rad/s$, this corresponds to about1.25ms. The same delay gives a larger phase error at a higher frequency.

A primary rotating-sensor experiment compared internal rotating MEMS sensors with stationary transmission-housing accelerometers; its analysis distinguishes rotating-frame spectral components and reconstruction of a rotation reference.^[ref] The calculation above is an illustrative correction model, not a measured error attributed to that apparatus. A whole-period delay cancels one ideal periodic component, but does not generally align transients or other frequencies.

A centripetal phase-error tolerance bounds the relative phase mismatch allowed when subtracting an oscillating centripetal correction. It translates an acceptable residual acceleration into a phase requirement and, for a known frequency, a timing requirement. With equal true and correction amplitudes $A>0$, a centripetal phase error $\varphi$ leaves residual amplitude $2A|\sin (\varphi /2)|$. For a budget $0\le E_{\max }<2A$, the permitted principal mismatch around zero isFor a pure time lag at angular frequency $\Omega >0$, divide this bound by $\Omega$ to obtain the lag tolerance. An allowable phase at one frequency is not a universal allowable delay for every spectral component.

For an original example, $A=4m/{\mathrm{s}}^2$ and $E_{\max }=0.10m/{\mathrm{s}}^2$ give a bound of about0.02500rad. At $\Omega =20rad/s$ this is approximately1.25ms; at $200rad/s$ it is approximately0.125ms. The tenfold change follows from the frequency dependence of phase delay, without changing the acceleration budget.

A centripetal amplitude-error budget is needed if the applied correction amplitude $\hat{A}$ differs from $A$. Phasor subtraction givesEven at zero phase error, the residual is at least $|\hat{A}-A|$. If that exceeds $E_{\max }$, timing improvement alone cannot meet the requirement. Otherwise, for positive amplitudes and a budget smaller than their sum, the allowed principal phase isWith $A=4$, $\hat{A}=3.96$ and budget0.10 in consistent acceleration units, the phase bound falls to about0.02303rad, or1.15ms at20rad/s.

The tolerance is a property of the correction model and the chosen operating range. A primary rotating MEMS-sensor study analyzes rotating-frame frequency components and reconstruction of a rotation reference; these are practical reasons to retain channel timing and phase information.^[ref] The numerical tolerances here are illustrative design calculations, not measured limits asserted for that apparatus.

Complex electrical power represents the active and reactive parts of sinusoidal electrical energy transfer in one complex number. Using phasors $V$ and $I$ whose magnitudes are root mean square values, with the passive sign convention, defineThe star denotes a complex conjugate. The real part is active power; the imaginary part is reactive power. The magnitude $|S|=|V||I|=\sqrt{P^2+Q^2}$ is apparent power. A source using peak-amplitude phasors instead has the factor $1/2$: $S=V_{\mathrm{peak}}{I}_{\mathrm{peak}}^{\ast }/2$.^[ref]

To see why the conjugate matters, write $V=|V|e^{j\alpha }$ and $I=|I|e^{j\beta }$. Then $S=|V||I|e^{j(\alpha -\beta )}$ depends on the relative phase. Changing the common time reference multiplies both phasors by $e^{j\theta }$, leaving $V{I}^{\ast }$ unchanged. The product $VI$ would instead acquire $e^{2j\theta }$ and would not represent a time-reference-independent average-power quantity.

For an original example, choose $V=100\mathrm{V}$ and $I=(4-j3)\mathrm{A}$. ThenThus active power is400W, reactive power is300 reactive volt-amperes and power factor is0.8. The corresponding electrical impedance is $V/I=16+j12\Omega$. With RMS current magnitude5A, the resistive term absorbs $16(5^2)=400\mathrm{W}$, agreeing with the real part.

Under the stated sign convention and $e^{j\omega t}$ time convention, an inductive reactance gives positive $Q$ and a capacitive reactance negative $Q$. Negative $Q$ does not mean a negative dissipated-energy average. For example, adding an ideal parallel capacitive branch contributing $-j300\mathrm{VA}$ cancels this example's reactive part, leaving terminal complex power400VA and RMS source current4A at100V, while the original resistive dissipation stays400W.

This one-frequency representation must not be applied indiscriminately to a distorted waveform. Different harmonics need their own phase relationships; the definition of active power remains the time average of the actual instantaneous power.

With $e^{i\omega t}$ phasors, critical damping gives $\Theta (\omega )=F_0/({\omega }_0+i\omega {)}^2$, amplitude $F_0/({\omega }_0^2+{\omega }^2)$ and phase $-2\arctan (\omega /{\omega }_0)$. The response strongly suppresses alternating currents well above the mechanical frequency.

The reciprocal of electrical impedance, relating electric current and electric potential difference phasors by $\tilde{I}=Y\tilde{V}$. Its unit is the siemens, $\mathrm{S}={\Omega }^{-1}$. Electrical admittances add for branches in a parallel circuit.

Electrical impedance is the ratio of terminal electric potential difference and electric current phasors at one specified positive angular frequency $\omega$. For an electrical circuit modeled as a linear time-invariant system, use the sinusoidal steady state after any decaying transient has settled. With the passive sign convention, positive electric current enters the terminal assigned positive electric potential difference. Define peak complex amplitudes byThe physical $v(t)$ and $i(t)$ are real; the complex numbers encode their amplitudes and wave phases. The unit of electrical impedance is the ohm, $1\Omega =1\mathrm{V}/\mathrm{A}$. Both phasors may instead use root mean square magnitudes, with the same ratio $Z$. A nonlinear diode can generate additional frequencies; a single $Z(\omega )$ then does not describe the whole response.

Write the electrical impedance in Cartesian and polar forms asHere $R$ is the resistive real part, $X$ the signed electrical reactance, and $\varphi$ the voltage-minus-current phase difference, defined modulo a full turn. The Pythagorean theorem gives the modulus from a right triangle in the complex plane. The complex argument gives the rotation from the current phasor to the voltage phasor. Thus $V_{\mathrm{rms}}=|Z|I_{\mathrm{rms}}$, while negative $\varphi$ means electric current leads terminal electric potential difference. For $R>0$, $\varphi =\arctan (X/R)$ lies between $-\pi /2$ and $\pi /2$; outside that case, use the quadrant of the complex number rather than a bare inverse tangent. The geometric magnitude and phase difference are the two pieces of the AC relation.^[ref]

Multiplication by $Z$ acts on phasors, not on instantaneous physical signals. For example, when $i(t)=I_0\cos \omega t$,The second term is in phase quadrature with electric current; it cannot be represented by pointwise multiplication $v(t)=Zi(t)$ when $X\ne 0$. This is the useful compression: one complex multiplication replaces separate amplitude and phase difference calculations, while the real part restores the physical signal.

An ideal resistor, inductor and capacitor have $Z_R=R$, $Z_L=\mathrm{i}\omega L$ and $Z_C=1/(\mathrm{i}\omega C)$. Their electrical impedances add in a series RLC circuit, giving $Z=R+\mathrm{i}(\omega L-1/(\omega C))$. The current amplitude is $V_0/|Z|$, so cancellation of the imaginary parts explains the resonant series RLC response. The component-law derivation and opposite complex exponential convention are in reactance phase convention.

An actual teaching experiment turns the phasor definition into readings. Leipzig University's laboratory handout Measurements with an oscilloscope, experiment E 3e, uses a function generator, a two-channel oscilloscope, a known resistor and a capacitor. Figure 5 places the capacitor above the resistor, with a common return below the resistor. Channel 1 measures the applied terminal electric potential difference $v_1$; channel 2 measures $v_R$. The handout asks for peak-to-peak values and relative timing, then comparison of measured and calculated electrical impedances with $R=3\mathrm{k\Omega }$, $C=0.47\mu \mathrm{F}$ at $100$ and $300\mathrm{Hz}$. It also asks students to check the oscilloscope time base against a digitally counted generator frequency. These are apparatus and procedural specifications, not reported measured results.^[ref]

For this arrangement, Ohm's law gives $i(t)=v_R(t)/R$ if probe loading and the sensing resistor's electrical reactance are negligible. Record both voltage magnitudes with the same convention: peak, peak-to-peak, or root mean square. After the transient settles, compare matched rising zero crossings $t_1$ of $v_1$ and $t_R$ of $v_R$, with period $T=1/f$. ThenThe recovered electrical impedance includes the known resistor. For a separate unknown component in series with that resistor, subtract $R$ from the inferred total electrical impedance. A current crossing earlier than the applied voltage crossing gives $\Delta t<0$, hence negative $\varphi$. For the stipulated series RC impedance example at $1000\mathrm{Hz}$, this predicts $\Delta t=-0.160717\mathrm{ms}$; it is a calculated timing, not a lab observation. Timing supplies the complex argument that an amplitude ratio alone cannot recover.

As additional measurement controls, first feed the same sinusoid to both channels to check relative delay and polarity; then replace the reactive chain with a known resistor, expecting nearly zero phase difference. Keep both probe returns at the common return shown in figure 5. A reversed voltage polarity adds half a turn to its inferred wave phase. Match crossings with the same slope and choose $-T/2<\Delta t\le T/2$; adjacent cycles otherwise change $\varphi$ by a full turn. A sweep continuous in frequency helps track that branch. These controls test the signed inference rather than assuming that the scope's delay readout has the desired sign.

Measure the loaded terminal electric potential difference on channel 1 at every frequency. The generator's output impedance can change the applied magnitude; its front-panel setting is not the measured terminal value. The generator's internal electrical impedance is outside the terminal ratio above, while the known sensing resistor is inside it. Probe loading, finite timing resolution, component tolerances and distorted waveforms limit the inference. A repeat at lower drive amplitude tests whether one linear electrical impedance still fits. Electrical reactance bench measurement develops these loading and reference-direction issues further.

In the $e^{i\omega t}$ phasor convention, electrical admittance is $Y=G+iB$, with conductance $G$ and electrical susceptance $B$. An ideal capacitor has $B=\omega C$ and an ideal inductor has $B=-1/(\omega L)$. electrical susceptances add for parallel branches; their cancellation gives a purely resistive input admittance.

The instantaneous rate of energy transfer through a circuit port is $P(t)=V(t)I(t)$, with positive electric current entering the positive voltage terminal for the passive sign convention. Peak phasors in sinusoidal steady state give $⟨P⟩=\frac{1}{2}\mathrm{Re}(\tilde{V}{\tilde{I}}^{\ast })$. The factor $1/2$ is absent for root mean square phasors.

With the noninverting input grounded, a differential input impedance $R_{\mathrm{in}}$ draws current from the summing node. For zero output impedance, $V_o=-Av$ and Kirchhoff's current law gives $(v-V_i)/R_1+(v-V_o)/R_2+v/R_{\mathrm{in}}=0$. Eliminating $v$ yields the displayed voltage gain. The resistor-ratio result requires $|A|\gg 1+R_2/R_1+R_2/R_{\mathrm{in}}$ as well as stable, unsaturated operation. The same expression applies to small-signal phasors with complex $A(f)$.

For $N$ equally spaced, coherently illuminated narrow slits at normal incidence, the phasor sum is proportional to $\sin (N\delta /2)/\sin (\delta /2)$, where $\delta =2\pi d\sin \theta /\lambda$. The first zero around the central maximum has $d\sin \theta =\lambda /N$. Principal maxima are removable zero-over-zero limits, not intensity zeros.

Electronic gain expresses how an electronic circuit scales a specified input signal quantity into an output quantity. For a linearized voltage amplifier around its operating point, the voltage gain is $A_v=\delta v_{\mathrm{out}}/\delta v_{\mathrm{in}}$. At a sinusoidal frequency it can be a complex phasor ratio, specifying both amplitude ratio and phase shift. Power gain instead compares the average power delivered to the load with the average signal power entering the amplifier:State the input/output quantities, frequency, load and operating conditions when specifying gain. A transimpedance amplifier relates output electric potential difference to input current and has a dimensional transfer ratio in ohms.

For an original circuit example, use an inverting operational amplifier with input resistor $R_1=10\mathrm{k\Omega }$, feedback resistor $R_2=100\mathrm{k\Omega }$ and load $R_L=1\mathrm{k\Omega }$. In its ideal negative-feedback linear regime,An input of $50\mathrm{mV}$ root mean square therefore gives $0.50\mathrm{V}$ root mean square at the output, with a phase inversion. The manufacturer's primary explanation derives this resistance-ratio gain using the input and feedback currents.^[ref] Suitable supplies, output-current capability and amplifier output range are assumptions of this worked model, not specifications of a particular device.

Here the input resistance is $R_1$ in the ideal model. For resistive ports and root-mean-square signal amplitudes,The example input power is $0.25\mu \mathrm{W}$ and load power $0.25\mathrm{mW}$, giving $G_P=1000$. The additional output energy comes from the amplifier's supply, controlled by the input signal. The impedance condition for converting voltage gain to power gain is essential: voltage magnitude alone does not specify load power.

Voltage gain is conventionally expressed as $20{\log }_{10}|A_v|$ decibels, while power gain uses $10{\log }_{10}{G}_P$. This example has voltage gain $20\mathrm{dB}$ and power gain $30\mathrm{dB}$; the two expressions agree when the resistive input and load impedances are equal. A negative voltage gain indicates phase inversion; its magnitude enters the logarithm.

A direct test drives a small sine wave into the input and measures the actual terminal signals with an oscilloscope. Sweeping frequency reveals the frequency response; increasing amplitude reveals amplifier clipping or other departure from the assumed linear gain. Keep the load and measurement impedances specified. Gain can amplify input noise along with signal, so the signal-to-noise ratio requires its own measurement.

Impedance bridging, also called voltage bridging, connects a source to a much higher load impedance so that little signal electric potential difference is lost across the source's output impedance. It is useful when the receiver should observe a signal while drawing little electric current from its source.

Represent a linear source at one frequency by open-circuit phasor $V_s$ and series electrical impedance $Z_s$. With receiving input impedance $Z_L$, the voltage divider givesThus $|Z_s/Z_L|\ll 1$ makes $H$ close to one as a complex number, controlling both amplitude and phase loading. For positive electrical resistances, the relative voltage loss is $R_s/(R_s+R_L)$. A $1\mathrm{k\Omega }$ source feeding $99\mathrm{k\Omega }$ retains $99\%$ of its open-circuit voltage; feeding $9\mathrm{k\Omega }$ retains $90\%$.

For a tolerance $\eta$ on that resistive relative loss,The often convenient ten-to-one ratio is therefore a chosen accuracy compromise, not a universal definition. A one-percent limit requires at least a ninety-nine-to-one ratio in this ideal resistive model. Voltage divider loading error gives the related loading problem when the source is itself a divider.

Impedance bridging with capacitive input explains why a large DC electrical resistance is not enough at every frequency. With source resistance $R_s$ and receiving $R_{\mathrm{in}}$ in parallel with capacitance $C_{\mathrm{in}}$,At $R_s=1\mathrm{k\Omega }$ and $R_{\mathrm{in}}=1\mathrm{M\Omega }$, the DC ratio is about $0.999$. With $C_{\mathrm{in}}=100\mathrm{pF}$, its magnitude at $1\mathrm{MHz}$ is only about $0.846$. The capacitive path loads the source despite the high DC input resistance.

Texas Instruments' three-amplifier presentation motivates high-input-impedance buffering by explicitly showing that source current and nonzero source output impedance degrade accuracy.^[ref] A buffer changes the load seen by the signal source; its own finite input and output behavior still matter.

Impedance matching has a different objective in maximum-power-transfer applications. For a resistive source, choosing equal source and load resistances gives half the open-circuit voltage, whereas bridging seeks a ratio near one. Signal fidelity, delivered power and high-frequency transmission behavior require their appropriate models.

Impedance bridging with capacitive input treats a receiver's input as a resistance in parallel with a capacitance. Even when its DC input impedance is large, the capacitive path can draw appreciable electric current at higher frequency, changing both the amplitude and phase of the observed electric potential difference.

For source resistance $R_s$, receiving resistance $R_{\mathrm{in}}$ and input capacitance $C_{\mathrm{in}}$, use sinusoidal steady-state phasors and a linear source model. The receiving electrical admittance is $1/R_{\mathrm{in}}+\mathrm{i}\omega C_{\mathrm{in}}$, soHere $V_s$ is the open-circuit source phasor; $V_L$ is the loaded terminal phasor. The impedance bridging objective is $H$ near one, rather than merely a large quoted DC input resistance.

The amplitude and phase responses areAn amplitude-only tolerance and a tolerance on the full complex number express different requirements. The latter measuresFor positive resistances, capacitance and a chosen $0<\eta <1$, the capacitive bridging complex-error bandwidth condition $|1-H|\le \eta$ requiresA negative numerator means even the DC loading error exceeds the tolerance.

In an original example, $R_s=1\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$ and $C_{\mathrm{in}}=100\mathrm{pF}$ give $g=0.001$. A one-percent complex-error tolerance permits frequencies only up to about $15.9\mathrm{kHz}$. At $100\mathrm{kHz}$ the amplitude ratio remains about $0.997$, but the phase is about $-3.59^{\circ }$ and the complex error about $0.0627$. A small amplitude error can coexist with a materially larger waveform-phase error.

High-input-impedance buffers are motivated by just this source-loading problem. Texas Instruments' three-amplifier presentation shows how current drawn from a source with finite output impedance degrades accuracy and how input buffers reduce loading.^[ref] The chosen component values above are not specifications of a particular amplifier. A real receiver may require additional input paths, frequency-dependent source impedance and a model of the connected cable or probe.

A voltage gain determines a power gain only when the electrical conditions at both ports are included. The familiar equality between $20{\log }_{10}|A_v|$ and $10{\log }_{10}{G}_P$ requires a particular impedance relation; it is not a conversion between arbitrary voltage and power ratios.

Use phasors whose moduli are root mean square amplitudes, at one sinusoidal frequency. At a load with electrical impedance $Z$ and electrical admittance $Y=1/Z$, the current is $I=YV$. Its complex electrical power is $V{I}^{\ast }$, with the complex conjugate arising from the relative phase of the two sinusoids. Averaging $v(t)i(t)$ over a cycle gives the active powerTo see the averaging step, write $v(t)=\sqrt{2}|V|\cos (\omega t+{\varphi }_V)$ and similarly for $i(t)$. The product's cycle average is $|V||I|\cos ({\varphi }_V-{\varphi }_I)$, the real part of $V{I}^{\ast }$. Peak-amplitude phasors instead require an extra factor $1/2$.

Let $Y_{\mathrm{in}}$ describe the actual input impedance and $Y_L$ the actual load impedance. Take $\mathrm{Re}{Y}_{\mathrm{in}}>0$ and $\mathrm{Re}{Y}_L>0$ with nonzero terminal signals, and define currents into the amplifier at the input and into the load at the output. With the measured loaded voltage gain $A_v=V_L/V_{\mathrm{in}}$,Thus $G_P=|A_v{|}^2$ requires equality of the relevant electrical conductances, not merely equality of impedance moduli. For example, input $Z_{\mathrm{in}}=50\Omega$ and load $Z_L=(30+40i)\Omega$ both have modulus $50\Omega$, but their electrical admittances have real parts $0.020$ and $0.012\mathrm{S}$. The multiplier is $0.6$, so $G_P=0.6|A_v{|}^2$.

For real resistive ports this becomesTake an original example with measured $|A_v|=0.5$, $R_{\mathrm{in}}=10\mathrm{k\Omega }$ and $R_L=50\Omega$. The voltage gain is $-6.02\mathrm{dB}$, while the power gain is $50$, or $16.99\mathrm{dB}$. An active buffer can reduce the signal's electric potential difference while delivering more signal power than it accepts at its input; the supply provides the additional energy.

The amplifier's output impedance is distinct from the connected load impedance. To show why that distinction matters, model its output by a Thévenin equivalent with open-circuit voltage $A_0{V}_{\mathrm{in}}$ and series resistance $R_o$. The voltage divider givesWith $A_0=0.6$ and $R_o=10\Omega$, the $50\Omega$ load produces the preceding $A_v=0.5$ example. Differentiating $R_L/(R_o+R_L{)}^2$ gives $(R_o-R_L)/(R_o+R_L{)}^3$, so delivered power is largest at $R_L=R_o$, as in the maximum power transfer theorem. Here its power gain is $90$. Increasing $R_L$ much further makes $A_v$ approach $A_0$ but reduces delivered power. That high-load-impedance regime is impedance bridging, useful for sensing the source's voltage with little loading.

A bench demonstration uses a function generator, a known termination and an oscilloscope. The Keysight guide explains that an expected-load setting changes how amplitude is displayed for generators with a fixed series output impedance; a high-impedance load can receive twice the voltage expected for a matched $50\Omega$ termination.^[ref] As an independent low-frequency resistive calculation, an open-circuit source of $1\mathrm{V}$ root mean square with $50\Omega$ series resistance delivers $0.5\mathrm{V}$ and $5\mathrm{mW}$ to $50\Omega$. Into $1\mathrm{M\Omega }$ it delivers about $0.99995\mathrm{V}$ but only $1.00\mu \mathrm{W}$. The larger terminal reading accompanies much less delivered power. Specify the actual load, frequency and amplitude convention when comparing gain measurements.

Input capacitance describes the capacitive part of an electrical port's small-signal input impedance, under stated bias, frequency, and termination conditions. In a simple parallel model with the $e^{i\omega t}$ convention, its electrical admittance isThe electric current drawn by the capacitance grows with angular frequency even if the DC input resistance is enormous. Analog Devices distinguishes differential input paths from common-mode paths to ground: a quoted capacitance must identify which terminals are driven and how the remaining circuit is connected.^[ref]

For an original loading example, let $R_{\mathrm{in}}=10\mathrm{M\Omega }$ and $C_{\mathrm{in}}=20\mathrm{pF}$. At $10\mathrm{MHz}$, the capacitive reactance magnitude is only $1/(2\pi f{C}_{\mathrm{in}})\approx 796\Omega$. A source with electrical resistance $R_s=1\mathrm{k\Omega }$ therefore has loaded-to-unloaded phasor ratioThe DC ratio is about $0.99990$. Thus a resistance-only reading would miss a substantial high-frequency amplitude reduction. The numbers are chosen examples, not a specification for a named device.

For this same model, the source-to-input time constant is $(R_s\Vert R_{\mathrm{in}})C_{\mathrm{in}}$ and the DC-normalized half-power signal bandwidth is its reciprocal divided by $2\pi$. A complex-error requirement is instead governed by capacitive bridging complex-error bandwidth; these specifications answer different questions.

For input capacitance inferred from measured admittance, apply a small sinusoidal electric potential difference, measure the input electric current and its phase shift, and infer $\mathrm{Im}(I/V)/\omega$ within the parallel-capacitance approximation. Fixture, cable, and probe capacitances contribute to the measured port unless removed or included explicitly. Dependence on bias or frequency can make a single fitted $C_{\mathrm{in}}$ an inadequate model.